mt90224 Zarlink Semiconductor, mt90224 Datasheet - Page 112

• Manufacturer Part Number: mt90224
• Description: 8-port Ima/tc Phy Device
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Synchronized access
Reset Value (Hex):
15:13
Bit #
Bit #
12
11
10
1:0
9
8
7
6
5
4
3
2
1
3
2
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
R/W
R/W
R
Unused. Read all 0’s.
This bit is set when the RX UTOPIA FIFO associated with a Link in non-IMA mode
overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for all cells (or all Stuff cells event)
associated with a link used in non-IMA mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Idle Cells associated with a link used in
non-IMA mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for Unassigned Cells associated with a link
used in non-IMA mode overflows. This bit is cleared by writing 0.
This bit is set when the UTOPIA Input counter for HEC Errored Cells associated with a link
used in non-IMA mode overflows. This bit is cleared by writing 0.
This bit is set when the TX TDM Link counter for all cells associated with a link overflows.
This bit is set when the TX TDM Link counter for Idle or Filler Cells associated with a link
overflows.
This bit is set when the TX TDM Link counter for TX Stuff Cells associated with a link
overflows.
This bit is set when the TX TDM Link counter for TX ICP Cells associated with a link
overflows.
This bit is set when the RX TDM Link counter for all cells (or all Stuff cells event)
associated with a link overflows.
This bit is set when the RX TDM Link counter for Idle or Filler Cells associated with a link
overflows.
This bit is set when the RX TDM Link counter for HEC Errored Cells associated with a link
overflows.
Value to write to the Enable bit. 1 to enable, 0 to mask interrupt. This value is transferred
when the bit 1:0 are 10.
0 will enable the transfer from the uP to the selected counter.
1 will enable the transfer from the selected counter to the uP.
00: Initialize all the counters with 0.
01: Initiate a read or write of the counter value.
10: Initiate a read or write of the IRQ enable counter bit.
11: Unused.
Table 87 - Counter Transfer Command Register (continued)
0x0410 - 0x041F (16 reg)
1 register per link. The RxClk and TxClk signals must be active for correct
register operation.
0000
0x040F (1 reg)
0080
Table 88 - IRQ Link TC Overflow Status Registers
Zarlink Semiconductor Inc.
MT90222/3/4
112
Description
Description
Data Sheet