cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 108

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

4.0 Segmentation Coprocessor
4.3 Segmentation Control and Data Structures
4.3.7 Segmentation Internal SRAM Memory Map
Table 4-27. Segmentation Internal SRAM Memory Map
4-28
0x1400
0x1408
0x14F8
0x1500
0x1508
0x15F8
0x1600
0x1640–0x174F
0x1750–0x17FF
Address
–
–
–
–
–
–
–
0x14FF
0x15FF
0x1407
0x140F
0x1507
0x150F
0x163F
SEG_SQ_QU0
SEG_SQ_QU1
SEG_SQ_QU31
SEG_TQ_QU0
SEG_TQ_QU1
SEG_TQ_QU31
Reserved
Reserved
Reserved
Segmentation Status Queue Base Table Registers (SEG_SQ_QUn):
Internal Transmit Queue Base Table Registers (SEG_TQ_QUn):
Name
As indicated in
range 0x1400–0x17FF.
address range 0x1400–0x14FF.
address range 0x1500–0x15FF.
0x1640–0x17FF.
The segmentation status queue base table registers (SEG_ST_QUn) are in the
The internal transmit queue base table registers (SEG_TQ_QUn) are in the
Other internal segmentation and scheduler registers are in the address range
Internal Segmentation and Scheduler Registers:
Mindspeed Technologies
Status Queue 0 Base Table
Status Queue 1 Base Table
Status Queue 31 Base Table
Transmit Queue 0 Base Table
Transmit Queue 1Base Table
Transmit Queue 31Base Table
Not implemented
Initialize to 0xFFFFFFFF
Not implemented
Table
4-27, the segmentation internal SRAM is in the address
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
Description
28237-DSH-001-C
CN8237