cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 99
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cn8237
Manufacturer Part Number
cn8237
Description
Atm Oc-12 Servicesar Plus With Xbr Traffic Management
Manufacturer
Mindspeed Technologies
Datasheet
1.CN8237.pdf
(415 pages)
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CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Figure 4-6. Segmentation Master Control Word
28237-DSH-001-C
4.3.4.2 Transmit Queue
Management
The transmit queues reside in a single continuous section of SAR SEG-shared
memory. During initialization the host configures the number of entries per queue
with the SEG_CTRL(TR_SIZE) field. The size ranges from 64 to 4096 entries
per queue. The host also selects a priority scheme at initialization with the
SEG_CTRL(TX_RND) bit. Both of these fields are static configurations and
must not be changed during runtime operation.
address of all active transmit queues. This register contains the base address of the
first queue, the number of active queues, and the write-only update interval for all
queues. A set of other internal registers, the Transmit Queue Base table entries,
track the current state of the queues.
the fields of these queues.
queue.
queue. The transmit queue base table contains all of the queue control variables
except for INTERVAL, which is located in the SEG_TXBASE register.
MSTR_CTRL
By initializing the SEG_TXBASE register, the host determines the base
The byte address of any transmit queue entry is given by:
The host manages each transmit queue as an independent write-only control
NOTE(S):
Control structures with only one double-word (64-bits) are transferred
as two 32-bit words, unless FORCE_64 is set.
DWORD
Value
Chapter 3.0
0
1
Mindspeed Technologies
(SEG_TXBASE(SEG_TXB) × 128) + <transmit queue number>
63
63
describes the runtime management of a write-only control
First Word
XXXX
× <decoded TQ_SIZE value> + <entry number> × 8
Access
32
64-Bit
32
31
31
First Word
READ_UD_PNTR (TxQ)
XXXX
Segmentation
Tables
0
0
™
4.3 Segmentation Control and Data Structures
4-13, 4-14, and
31
31
First Word
First Word
4.0 Segmentation Coprocessor
XXXX
XXXX
Access
32-Bit
0
0
4-15
below describe
8237_158
4-19
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