cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 263

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
28237-DSH-001-C
12.2 Unimplemented PCI Bus Interface
Functions
The PCI bus interface on the CN8237 does not implement all the transaction
types defined by the PCI bus specification; only those sections of the protocol
that are necessary for slave and DMA memory accesses are implemented. In
particular, the following transaction types are not implemented:
12.3 PCI Configuration Space
In accordance with the PCI Bus Specification, Revision 2.1, the CN8237 PCI bus
interface implements a 128-byte configuration register space. These
configuration registers can be used by the host processor to initialize, control, and
monitor the SAR bus interface logic. The complete definitions of these registers
and the relevant fields within them is given in the PCI bus specification, and will
not be repeated here. The descriptions and definitions of these register fields as
implemented in the CN8237 are shown in
8 KB depending on the value of the INCFIFO_SZ bit in the CONFIG1 register.
• The Dual Address Cycle command.
• Snooping and cache support. Memory Read Line, Memory Write, and
• Locked and exclusive accesses: the PCI LOCK* line is not driven by the
• I/O accesses (the I/O Read and I/O Write commands).
• Interrupt acknowledge cycles, including the Interrupt Acknowledge
• The Special Cycle command and Special Cycle transactions.
• Burst transfers that do not have simple, sequentially incrementing
The incoming DMA FIFO size is programmable and may be set to 2 KB or
Invalidate commands are internally aliased to the Memory Read and
Memory Write commands as per the PCI specification.
CN8237, and the PCI slave interface does not handle locked accesses by
other bus masters in any special manner.
command.
addresses for consecutive data phases. The PCI master logic always
performs sequentially incrementing burst transfers. The two LSBs of the
PCI address lines (AD[1,0]) must be 0 during the address phase of any
transfer made to the PCI slave logic (indicating sequentially incrementing
burst addresses). If AD[1,0] is not equal to 0, the slave logic signals a type
A or B target disconnect after the first data phase, forcing the external
master to perform a single word transfer as per the PCI specification.
Mindspeed Technologies
12.2 Unimplemented PCI Bus Interface Functions
™
Chapter
14.0.
12.0 PCI Bus Interface
12-3