cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 299

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
0x38
0x100
28237-DSH-001-C
31–10
29–27
21–16
7–0
Bit
Bit
31
30
26
25
24
23
22
9
8
—
—
Interrupt Delay Register (INT_DELAY)
Segmentation Control Register (SEG_CTRL)
Field
Size
22
Field
Size
1
1
8
1
1
3
1
1
1
1
1
6
Reserved
EN_TIMER
EN_STAT_CNT
STAT_CNT[7:0]
SEG_ENABLE
SEG_RESET
VBR_OFFSET
SEG_GFC
DBL_SLOT
CBR_TUN
ADV_ABR_TMPLT
USE_SCH_CTRL
Reserved
Name
14.3 Segmentation Registers
This register contains general control bits for the segmentation coprocessor. The
assertion of the HRST* system reset pin or GLOBAL_RESET bit in the
CONFIG0 register causes the clearing of the SEG_ENABLE control bit.
Name
Mindspeed Technologies
Set to 0.
Enable status queue interrupt timer delay.
Enable status queue interrupt counter delay.
Number of status queue entries written before allowing interrupt to
propagate to output pin.
Segmentation Enable—enables segmentation coprocessor. If disabled, the
segmentation coprocessor halts on a cell boundary.
Segmentation Reset—resets segmentation coprocessor and pointers.
Offset from schedule slot priority to general priority.
(VBR_OFFSET + (# VBR / ABR priorities)
USE_SCH_CTRL is asserted.
Enable segmentation GFC processing. The segmentation machine is
disabled when the SAR receives cells with GFC halt set. GFC priority
queues (set in the SCH_PRI register) are active for one cell for each
received cell with GFC SET_A bit = 1.
Each schedule slot occupies two words. Not active if USE_SCH_CTRL is
asserted.
Use first entry in each schedule slot for CBR/tunnel traffic.
Advanced ABR template mode. When logic high, per-connection MCR and
ICR enabled. When logic low, per-template MCR and ICR enabled.
Activate the use of SLOT_DEPTH, the 4-bit VBR_OFFSET field, and
TUN_PRI0_OFFSET from the SCH_CTRL register. De-activate the use of
DBL_SLOT and the 3-bit VBR_OFFSET field from the SEG_CTRL register.
Program and read as 0.
™
Description
Description
7.) Not active if
14.3 Segmentation Registers
14.0 CN8237 Registers
14-9