cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 361

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Figure 16-12. Recommended PCB Trace Layout Scheme
28237-DSH-001-C
Step 4 – Calculating the Data
Hold Time to the SAR
Recommendations
Conclusions and
Calculate the data hold time to the SAR:
plenty of margin in this design.
As is evident by the data presented thus far, the SAR (CN8237) Local Memory
interface requires attention to detail. The Local Memory interface is tightly timed
and requires that the clock signal(s) be delayed a minimum of 2.0 ns. The clock
delay may be accomplished with the use of a delay line (either active or passive).
Keeping all Local Memory PCB trace lengths to an absolute minimum and the
same relative length yields the optimal timing. This requires the memory chips to
be placed as close to the SAR device as possible. All of the Local Memory PCB
traces need to be of similar length (i.e., +/– 10%) with exception to the clock
line(s) which must be equal to the maximum Local Memory PCB trace length.
Figures 16-12
using by_16 SSRAM parts and populating two banks (per coprocessor). Two of
the SSRAM devices are placed on the same side of the board as the SAR and the
other two are placed on the back side of the board under the first two SSRAM
devices. The memory chips are connected to the pads at the ends of the L2 PCB
trace segments. The series terminator (Rs) should be placed as close to the (SAR)
source pin as is possible. The total signal trace length will be L1 + L2 with the bulk
of the trace length attributed to the L1 segment. In other words, route the traces
such that the L2 segments are kept to a minimum and insure that the two L2
segments are of equal length.
SAR
DL + FT1 + FT2 + (SSRAM data disable time) = data hold time to SAR
Assume the SSRAM minimum data disable time to be 0 ns.
2.375 ns + 0.8 ns + 0.8 ns = 3.975 ns
The SAR has a 0 ns minimum data hold time requirement; therefore, there is
Mindspeed Technologies
and
Rs
16-13
PCB
show a recommended PCB trace layout scheme when
L1
16.0 Electrical and Mechanical Specifications
™
L2
L2
8237_164
16.1 Timing
16-13