cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 351

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Figure 16-2. PCI Bus Output Timing Measurement Conditions
16.1.2 ATM Physical Interface Timing—UTOPIA and Slave UTOPIA
Table 16-3. UTOPIA Interface Timing Parameters (1 of 2)
28237-DSH-001-C
Symbol
t
t
t
high
t
cyc
low
su
TxCLK/RxCLK Cycle Time
TxCLK/RxCLK High Time
TxCLK/RxCLK Low Time
RxDATA Input Setup Time to RxCLK
RxPAR Input Setup Time to RxCLK
RxSOC (RxMARK) Input Setup Time to RxCLK
RxCLAV (RxFLAG*) Input Setup Time to RxCLK
TxCLAV (TxFLAG*) Input Setup Time to TxCLK
Three-state Output
Output Delay
All ATM physical interface signals are synchronous to the interface clocks,
TxCLK and RxCLK, except for TxCLAV (TxFLAG*) and RxCLAV (RxFLAG*)
in the slave UTOPIA mode. Timing parameters for the UTOPIA interface are
provided in
UTOPIA interface. Timing diagrams for both interfaces are provided in
Figures 16-3
NOTE:
Parameter
HCLK
When operating in UTOPIA 8-bit mode, RXDATA[8:15] are gated off.
However, these input signals are not terminated and float. These floating
signals may induce noise into the SAR and corrupt data received on the
UTOPIA Rx Interface. To fix this condition, add 50 k pull-ups to
RxDATA[8:15].
(1)
(1)
(1)
Mindspeed Technologies
(% of tcyc)
Table
(% of tcyc)
and 16-4.
(1)
t
(1)
on
16-3.
Table 16-4
(1)
(1)
(1)
t off
t val
provides the timing parameters for the slave
16.0 Electrical and Mechanical Specifications
™
Min
20
40
40
4
4
4
4
4
Max
—
60
60
—
—
—
—
—
16.1 Timing
Units
ns
ns
ns
ns
ns
ns
%
%
8237_104
16-3