cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 322

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

14.0 CN8237 Registers
14.7 PCI Bus Interface Registers
0x3a8—Host Interrupt Mask Register 1 (HOST_IMASK1)
14-32
28–27
23–16
10–3
Bit
31
30
29
26
25
24
15
14
13
12
11
2
1
0
Field
Size
1
1
1
2
1
1
1
8
1
1
1
1
1
8
1
1
1
EN_PCI_BUS_ERROR
Reserved
EN_TX_DISCARD
Reserved
EN_DMA_AFULL
EN_FR_PAR_ERR
EN_FR_SYNC_ERR
Reserved
EN_RSQUEUE_FULL
EN_RSM_OVFL
EN_RSM_HS_FULL
Reserved
EN_RSM_HF_EMPT
Reserved
EN_SEG_UNFL
EN_SEG_HS_FULL
Reserved
This register contains the interrupt enables that correspond to the status in the
HOST_ISTAT1 register. The assertion of the HRST* system reset pin clears all of
the HOST_IMASK1 interrupt enables.
14.7 PCI Bus Interface Registers
In accordance with the PCI Bus Specification, Revision 2.1, the SAR PCI bus
interface implements a 128-byte configuration register space. These
configuration registers are used by the host processor to initialize, control, and
monitor the PCI bus interface logic. The complete definitions of these registers
and the relevant fields within them are given in the PCI bus specification, and are
not repeated here. The implementation of the configuration space registers in the
CN8237 is shown in
other registers within the PCI configuration space.
Name
Mindspeed Technologies
Table
Enables interrupt when PCI_BUS_ERROR status is a logic 1.
Set to 0.
Enables interrupt when TX_DISCARD status is a logic 1.
Set to 0.
Enables interrupt when DMA_AFULL status is a logic 1.
Enables interrupt when FR_PAR_ERR status is a logic 1.
Enables interrupt when FR_SYNC_ERR status is a logic 1.
Set to 0.
Enables interrupt when RSQUEUE_FULL status is a logic 1.
Enables interrupt when RSM_OVFL status is a logic 1.
Enables interrupt when RSM_HS_FULL status is a logic high.
Set to 0.
Enables interrupt when RSM_HF_EMPT status is a logic high.
Set to 0.
Enables interrupt when SEG_UNFL status is a logic high.
Enables interrupt when SEG_HS_FULL status is a logic high.
Set to 0.
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
14-3.
Table 14-4
™
provides descriptions of fields and
Description
28237-DSH-001-C
CN8237