m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 294
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m37905
Manufacturer Part Number
m37905
Description
Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M37905.pdf
(565 pages)
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Fig. 11.4.1 Relationship between transfer clock and receive data
<1ST-8DATA-1SP>
(Receive data)
Error-permitted range of transfer baud
clock. (Refer to section “11.4.6 Receive operation.”) Accordingly, in order to receive data correctly,
the stop bit must be input when the transfer clock of one-set receive data rises last. Figure 11.4.1
shows the relationship between the transfer clock and receive data.
in order to receive data correctly.
make sufficient evaluation before actually using it.
During reception, the receive data input to the RxD
Accordingly, the transfer rate of the receiver and transmitter sides must satisfy the following formula
Be sure to satisfy the above formula, and set the timing with enough margin. Also, the user shall
RxD
i
Br: Transfer rate on receiver side (bps)
Bt: Transfer rate on transmitter side (bps)
F : BRGi’s count source frequency on receiver side (Hz)
b : Entire bit number of one-set data
Bt
1
When the transfer rate of
the receive data is slower
than the rate of the transfer
clock on the receiver side
When the transfer rate of
the receive data is faster
than the rate of the transfer
clock on the receiver side
(ex: 12 bits in the case of 1ST-8DATA-1PAR-2SP; See Figure 11.4.2.)
(b – 1) +
(Receiver side)
Transfer clock
F
1
<
1 period of BRGi’s count source (Maximum)
Br
1
According to the condition of the input timing,
a maximum of this period ( ) can be omitted.
7905 Group User’s Manual Rev.1.0
ST
ST
At the falling edge of ST, the transfer clock is
generated, and reception starts.
1 clock
(b – 0.5) +
11.4 Clock asynchronous serial I/O (UART) mode
D
D
0
0
1
F
9.5 clocks
<
i
8 clocks
pin is taken at the rising edge of the transfer
Bt
1
b
D
7
ST : Start bit
SP : Stop bit
D
7
SP
1 clock
SP
SERIAL I/O
SP must be detected at
this last rising edge of
the transfer clock.
11-39
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