m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 377

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

become inactive.) This state is called “wait mode.” (See Table 15.1.1.)
using no internal peripheral device in the wait mode, the power consumption can be saved furthermore since
each of f
of system clock in wait mode.”)
STOP AND WAIT MODES
15.4 Wait mode
15.4 Wait mode
When the WIT instruction is executed, both of
In the wait mode, the power consumption can be saved with Vcc (the power source voltage) retained. When
The wait mode is terminated owing to an interrupt request occurrence or hardware reset.
The wait mode terminate operation is described below.
15-12
Table 15.4.1 Interrupts which can be used for wait mode termination
Notes 1: When multiple interrupts are enabled, the wait mode is terminated owing to the interrupt request which
INT
Timer Ai interrupt (i = 0 to 9)
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0 to 2)
UARTi receive interrupt (i = 0 to 2)
A-D conversion interrupt
15.4.1 Terminate operation at interrupt request occurrence
Table 15.4.1 lists the interrupts which can be used for the wait mode termination.
Before executing the WIT instruction, be sure to enable an interrupt which is to be used for the wait mode
termination.
Also, make sure that the interrupt priority level of an interrupt, which is to be used for termination, is higher
than the processor interrupt priority level (IPL) of a routine where the WIT instruction is executed.
Also, when multiple interrupts in Table 15.4.1 are enabled, the wait mode is terminated owing to the
interrupt request which occurs first.
15.4.2 Terminate operation at hardware reset
Although each of the CPU and SFR area is initialized, the contents of the internal RAM immediately before
the WIT instruction execution are retained. The terminate sequence is the same as the internal processing
sequence after reset.
For reset, refer to “CHAPTER 3. RESET.”
Also, the WIT-instruction-execution status bit (bit 1 at address 63
• Which of the power-on reset and hardware reset has been used to reset the system?
• Has the hardware reset been used for the wait mode termination?
When an interrupt request occurs, each supply of
The interrupt request which occurred in
i
interrupt (i = 0 to 7)
2: For interrupts, refer to “CHAPTER 6. INTERRUPTS” and each peripheral device’s chapter.
sys
occurs first.
and internal peripheral device’s operation clock can be inactive. (Refer to section “16.2 Stop
Interrupt
7905 Group User’s Manual Rev.1.0
System clock in action
Usage conditions for interrupt request occurrences
is accepted.
CPU
and
CPU
BIU
and
become inactive. (The oscillation does not
BIU
16
starts.
) is used for the following verification:
In event counter mode
When an external clock is selected.
Do not use.
System clock out of action