m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 382
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m37905
Manufacturer Part Number
m37905
Description
Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M37905.pdf
(565 pages)
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Fig. 16.1.3 Structure of particular function select register 1
16.1.2 Particular function select register 1
Figure 16.1.3 shows the structure of the particular function select register 1.
(1) System clock stop select bit at WIT (bit 3)
Particular function select register 1 (Address 63
Notes 1: At power-on reset, this bit becomes “0.” At hardware reset or software reset, this bit retains the value just before reset.
Setting this bit to “1” makes the following clocks inactive in the wait mode: the operating clocks for
the internal peripheral devices and f
mode.”)
Bit
0
1
2
3
4
5
6
7
2: Even when “1” is written, the bit status will not change.
3: Setting this bit to “1” must be performed just before execution of the WIT instruction. Also, after the wait state is termi-
4: When using timer B2 in the pulse period/pulse width measurement mode, be sure to clear this bit to “0.”
nated, this bit must be cleared to “0” immediately.
STP-instruction-execution
status bit
WIT-instruction-execution
status bit
Fix this bit to “0.”
System clock stop select bit
at WIT
Fix this bit to “0.”
The value is “0” at reading.
Timer B2 clock source select bit
(Valid in event counter mode.)
The value is “0” at reading.
Bit name
(Note 3)
(Note 4)
7905 Group User’s Manual Rev.1.0
0 : External signal input to the TB2
1 : fX
0 : Normal operation.
1 : During execution of WIT instruction
0 : In the wait mode, system clock f
1 : In the wait mode, system clock f
0 : Normal operation.
1 : During execution of STP instruction
sys
. (Refer to section “16.2 Inactivity of system clock in wait
32
is counted.
16
POWER SAVING FUNCTIONS
)
Function
IN
pin is counted.
sys
sys
is active.
is inactive.
b7 b6 b5 b4 b3 b2 b1 b0
0
At reset
(Note 1)
(Note 1)
16.1 Overview
0
0
0
0
0
0
0
(Note 2)
(Note 2)
R/W
RW
RW
RW
RW
RW
RW
—
—
16-5
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