m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 494
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m37905
Manufacturer Part Number
m37905
Description
Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M37905.pdf
(565 pages)
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Part Number:
m37905F8CSP
Manufacturer:
MIT
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IMP
IMM
A
DIR
DIR, X
DIR, Y
(DIR)
(DIR, X)
(DIR), Y
L(DIR)
L(DIR), Y
ABS
ABS, X
ABS, Y
ABL
ABL, X
(ABS)
L(ABS)
(ABS, X)
STK
REL
DIR, b, R
ABS, b, R
SR
(SR), Y
BLK
Multiplied
accumulation
op
n
#
C
Z
I
D
x
m
V
N
IPL
+
–
÷
| |
Acc
Acc
Acc
A
A
A
B
B
B
H
L
H
L
Symbol
H
L
Implied addressing mode
Immediate addressing mode
Accumulator addressing mode
Direct addressing mode
Direct indexed X addressing mode
Direct indexed Y addressing mode
Direct indirect addressing mode
Direct indexed X indirect addressing mode
Direct indirect indexed Y addressing mode
Direct indirect long addressing mode
Direct indirect long indexed Y addressing mode
Absolute addressing mode
Absolute indexed X addressing mode
Absolute indexed Y addressing mode
Absolute long addressing mode
Absolute long indexed X addressing mode
Absolute indirect addressing mode
Absolute indirect long addressing mode
Absolute indexed X indirect addressing mode
Stack addressing mode
Relative addressing mode
Direct bit relative addressing mode
Absolute bit relative addressing mode
Stack pointer relative addressing mode
Stack pointer relative indirect indexed Y addressing
mode
Block transfer addressing mode
Multiplied accumulation addressing mode
Instruction code (Op code)
Number of cycles
Number of bytes
Carry flag
Zero flag
Interrupt disable flag
Decimal operation mode flag
Index register length selection flag
Data length selection flag
Overflow flag
Negative flag
Processor interrupt priority level
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
Logical exclusive OR
Absolute value
Negation
Movement to the arrow direction
Movement to the arrow direction
Exchange
Accumulator
Accumulator’s high-order 8 bits
Accumulator’s low-order 8 bits
Accumulator A
Accumulator A’s high-order 8 bits
Accumulator A’s low-order 8 bits
Accumulator B
Accumulator B’s high-order 8 bits
Accumulator B’s low-order 8 bits
Description
7905 Group User’s Manual Rev.1.0
E
E
E
X
X
X
Y
Y
Y
S
REL
PC
PC
PC
PG
DT
DPR0
DPR0
DPR0
DPRn
DPRn
DPRn
PS
PS
PS
PS
M
M(S)
M(bit n)
Mn
IMM
IMMn
IMM
IMM
AD
AD
AD
EAR
EAR
EAR
imm
imm
dd
i
i
source
dest
1
, i
H
L
H
L
H
L
Symbol
H
L
L
2
H
L
H
M
L
(bit n)
n
H
L
H
L
H
L
H
L
Appendix 6. Machine instructions
Accumulator E
Accumulator E’s high-order 16 bits (Accumulator B)
Accumulator E’s low-order 16 bits (Accumulator A)
Index register X
Index register X’s high-order 8 bits
Index register X’s low-order 8 bits
Index register Y
Index register Y’s high-order 8 bits
Index register Y’s low-order 8 bits
Stack pointer
Relative address
Program counter
Program counter’s high-order 8 bits
Program counter’s low-order 8 bits
Program bank register
Data back register
Direct page register 0
Direct page register 0’s high-order 8 bits
Direct page register 0’s low-order 8 bits
Direct page register n
Direct page register n’s high-order 8 bits
Direct page register n’s low-order 8 bits
Processor status register
Processor status register’s high-order 8 bits
Processor status register’s low-order 8 bits
nth bit in processor status register
Contents of memory
Contents of memory at address indicated by stack
pointer
nth bit of memory
n-bit memory’s address or contents
Immediate value (8 bits or 16 bits)
n-bit immediate value
16-bit immediate value’s high-order 8 bits
16-bit immediate value’s low-order 8 bits
Value of 24-bit address’s high-order 8 bits (A
Value of 24-bit address’s middle-order 8 bits (A
Value of 24-bit address’s low-order 8 bits (A
Effective address (16 bits)
Effective address’s high-order 8 bits
Effective address’s low-order 8 bits
8-bit immediate value
n-bit immediate value
Displacement for DPR (8 bits or 16 bits)
Number of transfer bytes, rotation or repeated operations
Number of registers pushed or pulled
Operand to specify transfer source
Operand to specify transfer destination
Description
APPENDIX
7
23
–A
–A
15
0
)
–A
16
)
8
)
20-63
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