m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 436

• Manufacturer Part Number: m37905
• Description: Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
• Manufacturer: Renesas Electronics Corporation.

Address
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access characteristics
State immediately after reset
Notes 7 : By writing dummy data to address 60
WO
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
RW
16
16
16
16
16
16
16
16
RO
16
16
16
16
0
1
?
Watchdog timer frequency select register
Particular function select register 0
Particular function select register 1
Particular function select register 2
10 : It is possible to read the bit state at reading. By writing “0” to this bit, this bit becomes “0.”
11 : This bit becomes “0” at power-on reset. This bit retains the state immediately before reset in the case of
12 : Do not write to this register.
13 : When these registers are accessed, set the address comparison register access enable bit (bit 2 at address
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
UART0 transmit interrupt control register
UART1 transmit interrupt control register
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after
A-D conversion interrupt control register
UART0 receive interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
8 : A value of “FFF
9 : After writing “55
reset.
Address comparison register 0
Address comparison register 1
INT
INT
INT
INT
INT
hardware reset and software reset.
67
The dummy data is not retained anywhere.
But when writing “1” to this bit, this bit will not change.
Watchdog timer register
0
1
2
Debug control register 0
Debug control register 1
3
4
16
interrupt control register
interrupt control register
interrupt control register
interrupt control register
interrupt control register
) to “1.” (Refer to “CHAPTER 17. DEBUG FUNCTION.”)
Register name
16
16
” is set to the watchdog timer. (Refer to “CHAPTER 14. WATCHDOG TIMER.”)
” to address 62
7905 Group User’s Manual Rev.1.0
b7
RW RW
16
0
1
?
0
, each bit must be set.
RW
16
RO
: Always “0” at reading.
: Always “1” at reading.
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
Access characteristics
, a value of “FFF
RO
RW
RW (Note 13)
RW (Note 13)
RW (Note 13)
RW (Note 13)
RW (Note 13)
RW (Note 13)
Appendix 1. Memory assigment in SFR area
(Note 12)
RW
(Note 7)
RW
RW
RW
RW
RW
RW
RW
RW
16
RW
RW
” is set to the watchdog timer.
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW (Note 9)
(Note 10)
RO
RW
RW
b0
b7
0
0
0
1
0
State immediately after reset
?
?
?
?
?
0
0
0
0
0
?
?
?
?
?
?
?
?
?
?
?
?
?
(Note 11)
0
0
0
0
0
0
0
0
? (Note 8)
?
0
0
0
0
0
0
0
0
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
APPENDIX
0
0
(Note 11)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(Note 11)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
b0
20-5