m37905 Renesas Electronics Corporation., m37905 Datasheet - Page 323
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m37905
Manufacturer Part Number
m37905
Description
Mitsubishi 16-bit Single-chip Microcomputer 7700 Family / 7900 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M37905.pdf
(565 pages)
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A-D CONVERTER
12.2 Block description
12-12
Fig. 12.2.7 Structures of comparator function select register 0 and 1
12.2.3 Comparator function select register 0, 1 and comparator result register 0, 1
Figure 12.2.7 shows the structures of comparator function select register 0 and 1; Figure 12.2.8 shows the
structures of comparator result register 0 and 1.
When the AN
the A-D conversion is performed, be sure to clear the corresponding bit to “0.”
For details of the comparator function, refer to section “12.6 Comparator function.”
Comparator function select register 0 (Address DC
Note: Writing to comparator function select register 0 must be performed while the A-D converter halts.
Comparator function select register 1 (Address DD
Note: Writing to comparator function select register 1 must be performed while the A-D converter halts.
7 to 4
Bit
Bit
0
1
2
3
4
5
6
7
0
1
2
3
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
Fix these bits to “0000.”
i
pin comparator function select bit is set to “1,” the comparator function is selected. When
0
1
2
3
4
5
6
7
8
9
10
11
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
pin comparator function select bit
Bit name
Bit name
7905 Group User’s Manual Rev.1.0
0 : The comparator function is not selected.
1 : The comparator function is selected.
0 : The comparator function is not selected.
1 : The comparator function is selected.
16
16
)
)
Function
Function
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
At reset
0
At reset
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
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