PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 18

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8811_4
Product data sheet
7.1.19.3 DB3 and DB2 (I
7.1.20 OSC: oscillator
7.1.21 RES: reset
7.2.1 Oscillator
7.2.2 Address counter
7.2.3 Display data RAM
7.2.4 Timing generator
7.2 Block diagram functions
DB3 and DB2 are respectively the SA1 and SA0 inputs when the I
selected and can be used so that up to four PCF8811s can be distinguished on one
I
This signal will reset the device and must be applied to properly initialize the chip. The
signal is active LOW.
See
The on-chip oscillator provides the clock signal for the display system. No external
components are required, and the OSC input must be connected to V
clock signal, if used, is connected to this input.
The address counter assigns addresses to the display data RAM for writing. The X
address X[6:0] and the Y address Y[3:0] are set separately.
The PCF8811 contains an 80
The timing generator produces the various signals required to drive the internal circuitry.
Internal chip operation is not affected by operations on the data bus.
2
C-bus interface.
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•
•
•
•
•
•
When the on-chip oscillator is used this input must be connected to V
If an external clock signal is used, it is connected to this input
If the oscillator and an external clock are both inhibited by connecting the OSC pad to
V
avoid a DC on display, the chip should always be put into Power-down mode before
stopping the clock
The RAM is divided into 10 banks of 128 bytes (10
The icon row (when enabled) is always row 79 and located in bank 9
During RAM access, data is transferred to the RAM via the parallel interface, serial
interface or I
There is a direct correspondence between the X address and the column output
number
Figure 1
SS1
, the display is not clocked and may be left in a Direct Current (DC) state. To
for the block diagram layout.
2
2
C-bus interface)
C-bus interface
Rev. 04 — 27 June 2008
128 bit static RAM which stores the display data.
80 x 128 pixels matrix LCD driver
8
128 bit)
2
C-bus interface is
DD1
PCF8811
© NXP B.V. 2008. All rights reserved.
. An external
DD1
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