PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 45

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8811_4
Product data sheet
12.5.2 Bit MY
12.6 Set Y address of RAM
12.7 Set X address of RAM
12.8 Set display start line
When MX = 1 the display RAM is written from right to left (X = 0 is on the right side and
X = X
The MX bit has an impact on the way the RAM is written to. So if a horizontal mirroring of
the display is desired, the RAM must first be rewritten, after changing the MX bit.
When MY = 1, the display is mirrored vertically. A change to this bit has an immediate
effect on the display.
Y[3:0] defines the Y address of the display RAM.
Table 22.
When the icon row (row 79) is enabled it will always be in bank 9 independent of the
multiplex rate which is programmed.
The X address points to the columns. The range of X is 0 to 127 (7Fh).
L[6:0] (see
displayed on the initial row, row 0. The selection of L[6:0] is limited to steps of 8. When the
icon row is selected, the selection of L[6:0] is limited to steps of 16. When a partial mode
is selected, the selection of L[6:0] is also limited in steps. In addition, the selection of
L[6:0] = 72 is not allowed when the icon row is enabled or disabled.
The initial row can, in turn, be set by C[6:0]; see
79 when enabled.
An example of the mapping from the RAM content to the display is shown in
The content of the RAM is not modified. This feature allows, for instance, screen scrolling
without rewriting the RAM.
Y3
0
0
0
0
0
0
0
0
1
1
max
is on the left side of the display).
Y2
0
0
0
0
1
1
1
1
0
0
RAM X/Y address range
Table
11) is used to select the display line address of the display RAM to be
Y1
0
0
1
1
0
0
1
1
0
0
Rev. 04 — 27 June 2008
Y0
0
1
0
1
0
1
0
1
0
1
Content
bank 0 (display RAM)
bank 1 (display RAM)
bank 2 (display RAM)
bank 3 (display RAM)
bank 4 (display RAM)
bank 5 (display RAM)
bank 6 (display RAM)
bank 7 (display RAM)
bank 8 (display RAM)
bank 9 (display RAM)
Table
11. Row 0 cannot be set to icon row
80 x 128 pixels matrix LCD driver
Allowed X range
0 to 127
0 to 127
0 to 127
0 to 127
0 to 127
0 to 127
0 to 127
0 to 127
0 to 127
0 to 127
PCF8811
© NXP B.V. 2008. All rights reserved.
Figure
45 of 81
33.