PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 32

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8811_4
Product data sheet
11.1.2 Bit transfer
11.1.3 Start and stop conditions
11.1.4 Acknowledge
One data bit is transferred during each clock pulse; see
line must remain stable during the HIGH period of the clock pulse as changes in the data
line at this time will be interpreted as a control signal.
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are shown in
Each byte of eight bits is followed by an acknowledge bit; see
bit is a HIGH signal put on the bus by the transmitter during which time the master
generates an extra acknowledge-related clock pulse. A slave receiver which is addressed
must generate an acknowledge after the reception of each byte. A master receiver must
also generate an acknowledge after the reception of each byte that has been clocked out
of the slave transmitter. The device that acknowledges must pull-down the SDA line during
the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period
Fig 25. System configuration
Fig 26. Bit transfer
Fig 27. Definition of START and STOP conditions
SCL
SDA
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
START condition
SDA
SCL
S
Rev. 04 — 27 June 2008
RECEIVER
SLAVE
data valid
data line
stable;
TRANSMITTER/
RECEIVER
SLAVE
allowed
change
of data
80 x 128 pixels matrix LCD driver
TRANSMITTER
Figure
MASTER
Figure
Figure
STOP condition
26. The data on the SDA
mbc621
P
28. The acknowledge
27.
PCF8811
TRANSMITTER/
© NXP B.V. 2008. All rights reserved.
RECEIVER
MASTER
mbc622
mga807
SDA
SCL
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