PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 72

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 38.
[1]
PCF8811_4
Product data sheet
Instruction
CALMM
Power control
(‘refresh’)
Fig 52. Basic OTP architecture
X = value without meaning.
Additional interface commands
read data
OTP cell
from the
18.1.5.1 CALMM
18.1.5.2 Refresh
18.1.5 Interface commands
Pad
EXT
X
X
[1]
[1]
REGISTER
FLIP-FLOP
OTP CELL
OTP slice
SHIFT
D/C
0
0
These instructions are in addition to those indicated in
This instruction puts the device in calibration mode. This mode enables the shift register
for loading and allows programming of the non-volatile OTP cells to take place. If the seal
bit is set then this mode cannot be accessed and the instruction will be ignored. Once in
calibration mode all commands are interpreted as shift register data. The mode can only
be exited by sending data with DB7 set to logic 0. Reset will also clear this mode. Each
shift register data byte is preceded by D/C = 0 and has only 2 significant bits, thus the
remaining 6 bits are ignored. DB7 is the continuation bit (DB7 = 1 remain in CALMM
mode, DB7 = 0 exit CALMM mode). DB0 is the data bit and its value is shifted into the
OTP shift register (on the falling edge of SCLK).
The action of the ‘Refresh’ instruction is to force the OTP shift register to re-load from the
non-volatile OTP cells. This instruction takes up to 5 ms to complete. During this time all
other instructions may be sent.
In the PCF8811 the ‘Refresh’ instruction is associated with the ‘Power control’ instruction
so that the shift register is automatically refreshed every time the high voltage multiplier is
enabled or disabled. Note that if this instruction is sent while in Power-save mode, the
PC[1:0] bits are updated but the refreshing is ignored.
write data
to the
OTP cell
R/W/WR DB7
0
0
REGISTER
INPUT
SHIFT
DATA
Command byte
1
0
DB6
0
0
Rev. 04 — 27 June 2008
DB5
0
1
CONFIGURATION AND CALIBRATION
DB4
0
0
DATA TO THE CIRCUIT FOR
DB3
0
1
DB2
PC1
0
DB1
PC0
1
80 x 128 pixels matrix LCD driver
Table
DB0
0
1
10.
Description
enter CALMM mode
switch HVgen on/off to
force a refresh of the shift
register
PCF8811
SHIFT
REGISTER
OTP CELLS
© NXP B.V. 2008. All rights reserved.
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