PCF8811U/2DA/1 NXP [NXP Semiconductors], PCF8811U/2DA/1 Datasheet - Page 71

• Manufacturer Part Number: PCF8811U/2DA/1
• Description: 80 x 128 pixels matrix LCD driver
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8811_4
Product data sheet
18.1.4 OTP architecture
The OTP circuitry in the PCF8811 contains 9 bits of data: 5 for V
(MMVOPCAL), 3 for the temperature coefficient default setting in the basic command set
MMTC and 1 seal bit. The circuitry for 1-bit is called an OTP slice. Each OTP slice
consists of 2 main parts: the OTP cell (a non-volatile memory cell) and the shift register
cell (a flip-flop). The OTP cells are only accessible through their shift register cells: on the
one hand both reading from and writing to the OTP cells is performed with the shift
register cells, on the other hand only the shift register cells are visible to the rest of the
circuit. The basic OTP architecture is shown in
This OTP architecture allows the following operations:
Reading data from the OTP cells — The content of the non-volatile OTP cells is
transferred to the shift register where upon it may affect the PCF8811 operation.
Writing data to the OTP cells — All 9 data bits are shifted into the shift register via the
interface. The content of the shift register is then transferred to the OTP cells. There are
some limitations related to storing data in these cells; see
Checking calibration without writing to the OTP cells — Shifting data into the shift
register allows the effects on the V
The reading of data from the OTP cells is initiated by either:
Remark: Note that in both cases the reading operation needs up to 5 ms to complete.
The shifting of data into the shift register is performed in the special mode CALMM. In the
PCF8811 the CALMM mode is entered by the CALMM command. Once in the CALMM
mode the data is shifted into the shift register via the interface at the rate of 1-bit per
command. After transmitting the last (9
interface will return to the normal mode and all other commands can be sent. Care should
be taken that 9 bits of data (or a multiple of 9) are always transferred before exiting the
CALMM mode, otherwise the bits will be in the wrong positions.
In the shift register the value of the seal bit is, like the others, always zero at reset. To
ensure that the security feature (seal bit) works correctly, the CALMM command is
disabled until a refresh has been performed. Once the refresh is completed, the seal bit
value in the shift register will be valid and permission to enter the CALMM mode can thus
be determined.
The 9 bits are shifted into the shift register in a predefined order: first 5 bits of
MMVOPCAL[4:0], 3 bits for MMTC[2:0] and lastly the seal bit. The MSB is always first,
thus the first bit shifted is MMVOPCAL[4] and the two last bits are MMTC[0] and the seal
bit.
•
•
Exit from Power-save mode
The ‘Refresh’ command (power control)
Rev. 04 — 27 June 2008
LCD
voltage to be observed.
th
) bit and exiting the CALMM mode, the serial
Figure
80 x 128 pixels matrix LCD driver
52.
Section
LCD
18.1.7.
calibration
PCF8811
© NXP B.V. 2008. All rights reserved.
71 of 81