DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 14

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
10. Application information
DAC1617D1G0 3
Preliminary data sheet
10.2.1 Protocol description
10.1 General description
10.2 Serial Peripheral Interface (SPI)
The DAC1617D1G0 is a dual 16-bit DAC operating up to 1000 Msps. Each DAC consists
of a segmented architecture, comprising a 6-bit thermometer subDAC and a 10-bit binary
weighted subDAC.
A maximum input LVDS DDR data rate of up to 370 MHz and a maximum output sampling
rate of 1000 Msps ensure more flexibility for wide bandwidth and multi-carrier systems.
The internal 40-bit NCO of the DAC1617D1G0 simplifies the frequency selection of the
system. The DAC1617D1G0 provides 2, 4 or 8 interpolation filters that are useful for
removing the undesired images.
Each DAC generates two complementary current outputs on pins IOUTAP and IOUTAN
and pins IOUTBP and IOUTBN. These outputs provide a full-scale output current (I
up to 34 mA. An internal reference is available for the reference current which is externally
adjustable using pin VIRES.
High resolution internal gain, phase and offset control provide outstanding image and
Local Oscillator (LO) signal rejection at the system analog modulator output.
Multiple device synchronization enables synchronization of the outputs of multiple DAC
devices. MDS guarantees a maximum skew of one output clock period between several
devices.
All functions can be set using an SPI interface.
The DAC1617D1G0 serial interface is a synchronous serial communication port ensures
easy interface with many industry microprocessors. It provides access to the registers that
define the operating modes of the chip in both write and read mode.
This interface can be configured as a 3-wire type (pin SDIO as bidirectional pin) or 4-wire
type (pins SDIO and SDO as unidirectional pins, input and output port, respectively). In
both configurations, SCLK acts as the serial clock and SCS_N as the serial chip select.
Figure 3 shows the SPI protocol. An SCS_N signal follows each read/write operation. A
LOW assertion enables it to drive the chip with 2 bytes to 5 bytes, depending on the
content of the instruction byte (see Table 7).
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
DAC1617D1G0
© IDT 2012. All rights reserved.
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