DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 38

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
10.16 Limiter/clip control
10.17 Digital offset adjustment
10.18 Analog output
A limiter at the end of the data path saturates the output signal in case the signal does not
fit the output range. This feature is activated using the CLIPPING_ENA bit in register
DAC_OUT_CTRL (see Table 28).
The clipping level can be programmed using the CLIPPING_LEVEL register
(see Table 29.). The output range is limited (or clipped) to between
128x CLIPPING_LEVEL and +128x CLIPPING_LEVEL.
At the DAC analog output, the AC current range is limited to:
The DAC1617D1G0 provides digital offset correction (bits DAC_A_OFFSET[15:0] in
Table 30). This correction can be used to adjust the common-mode level at the output of
each DAC. It adds an offset at the end of the digital part, just before the DACs. Table 18
shows the range of variation of the digital offset.
This offset can be used to remove the LO image at the IQ modulator output.
Table 18.
The device has two output channels, producing two complementary current outputs,
which enable the reduction of even-order harmonics and noise. The pins are
IOUTAP/IOUTAN and IOUTBP/IOUTBN. Connect these pins via a load resistor R
3.3 V analog power supply (V
Figure 28 shows the equivalent analog output circuit of one DAC. This circuit includes a
parallel combination of NMOS current sources and associated switches for each
segment.
–
DAC_A_OFFSET[15:0]
DAC_B_OFFSET[15:0]
(two’s complement)
1000 0000 0000 0000
1000 0000 0000 0001
...
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0001
...
0111 1111 1111 1110
0111 1111 1111 1111


I
--------------
O FS

2




Digital offset adjustment


CLIPPING_LEVEL
--------------------------------------------------- -
256
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
DDA(3V3)



I
IOUT
).

+


Offset applied
32768
32767
...
1
0
+1
...
+32766
+32767
I
------------- -
O FS

2






CLIPPING_LEVEL
--------------------------------------------------- -
DAC1617D1G0
256
© IDT 2012. All rights reserved.
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