DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 70

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
Table 62.
Default values are shown highlighted.
DAC1617D1G0 3
Preliminary data sheet
Address
0Ch
0Dh
0Eh
0Fh
LDS/MDS of I/Q DC levels registers (address 0Ch to 0Fh) bit description
Register
I_DC_LVL_LSB
I_DC_LVL_MSB
Q_DC_LVL_LSB
Q_DC_LVL_MSB
Table 63.
Default values are shown highlighted.
IO_SELECT0[9:0]
00 0000 0000
00 0000 0001
01 0000 nnnn
10 0000 1111
10 0001 1111
10 0010 1111
10 0011 1111
11 1100 0000
11 1100 0001
11 1111 1110
11 1111 1111
Bit
7 to 0
7 to 0
7 to 0
7 to 0
Register IO_MUX0 and IO_MUX2 (address 10h and 12h)
Symbol
I_DC_LEVEL[7:0]
I_DC_LEVEL[15:8]
Q_DC_LEVEL[7:0]
Q_DC_LEVEL[15:8]
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Signal on pin IO0
lclk
ringo
Ldout_A<nnnn>
AND (Ldout_B bits)
OR (Ldout_B bits)
AND (Ldout_A bits)
OR (Ldout_A bits)
INTR
INTR
1
0
Access
R/W
R/W
Value
-
-
-
-
Description
I_DC_LEVEL
Q_DC_LEVEL
least significant 8 bits for
I_DC_LEVEL
most significant 8 bits for
I_DC_LEVEL
least significant 8 bits for
Q_DC_LEVEL
most significant 8 bits for
Q_DC_LEVEL
DAC1617D1G0
Description
internal LVDS lclk clock
internal low frequency oscillator
(approximately 1 MHz)
internal LVDS data bit of
channel A (<nnnn> = 15 to 0;
enabling the selection of the bit
number to be observed)
AND result of the 16 LVDS data
bits of channel B
OR result of the 16 LVDS data
bits of channel B
AND result of the 16 LVDS data
bits of channel A
OR result of the 16 LVDS data
bits of channel A
active low interrupt signal
active high interrupt signal
set the general-purpose IO to
high level
set the general-purpose IO to
low level
© IDT 2012. All rights reserved.
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