DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 31

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
10.11.4 Minus 3dB
10.12 Inverse (sin x) / x
10.13 Multiple Devices Synchronization (MDS)
In normal use, a full-scale pattern is also full-scale at the DAC output. Nevertheless, when
the I data and Q data come close to full-scale simultaneously, some clipping can occur.
The Minus 3dB function (bit MINUS_3DB of register DAC_OUT_CTRL; see Table 28) can
be used to reduce the 3 dB gain in the modulator. It retains a full-scale range at the DAC
output without added interferers.
A selectable FIR filter is incorporated to compensate the (sin x) / x effect caused by the
roll-off effect of the DAC. This filter has no effect at DC. It introduces a gain for high
frequency. The coefficients are represented in Table 16. The filter response is presented
in Figure 22.
Table 16.
Several DAC channels can be sampled synchronously and phase coherently using the
MDS feature.
When all DAC slave devices of one system receive the same MDS signal (or at least a
synchronous version of this reference) all devices are time-aligned at 1 DAC clock
accuracy at the end of the synchronization process.
Lower
H(1)
H(2)
H(3)
H(4)
H(5)
Fig 22. Inverse (sin x) / x response
Inversion filter coefficients
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Upper
H(9)
H(8)
H(7)
H(6)
-
First interpolation filter
DAC1617D1G0
Value
+1
4
+13
51
+610
© IDT 2012. All rights reserved.
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