DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 77

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
16. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Folded and interleaved format mapping . . . . . .19
Table 11. CDI mode 0: operating modes examples . . . .25
Table 12. CDI mode 1: operating modes examples . . . .25
Table 13. CDI mode 2: operating modes examples . . . .26
Table 14: Interpolation filter coefficients . . . . . . . . . . . . .27
Table 15. Complex modulator operation mode . . . . . . . .30
Table 16. Inversion filter coefficients . . . . . . . . . . . . . . . .31
Table 17. DAC transfer function . . . . . . . . . . . . . . . . . . .36
Table 18. Digital offset adjustment . . . . . . . . . . . . . . . . .38
Table 19. Auxiliary DAC transfer function . . . . . . . . . . . .40
Table 20. SPI start-up sequence . . . . . . . . . . . . . . . . . . .46
Table 21. Page_00 register allocation map . . . . . . . . . . .48
Table 22. Register COMMON (address 00h)
Table 23. Register TXCFG (address 01h)
Table 24. Register PLLCFG (address 02h)
Table 25. NCO frequency registers (address 04h to 08h)
Table 26. DAC output phase correction registers
Table 27. Digital gain control registers (address 0Bh to 0Eh)
Table 28. Register DAC_OUT_CTRL (address 0Fh) . . .52
Table 29. Register DAC_CLIPPING (address 10h) . . . . .53
Table 30. Digital offset value registers (address 11h to 14h)
Table 31. NCO phase offset registers (address 15h to 16h)
Table 32. Analog gain control registers (address 17h to 1Ah)
Table 33. Auxiliary DAC registers (address 1Bh to 1Eh)
Table 34. SPI_PAGE register (address 1Fh)
Table 35. Page 1 register allocation map . . . . . . . . . . . .55
Table 36. MDS_MAIN register (address 00h)
Table 37. MDS window time registers (address 01h to 02h)
Table 38. MDS_MISCCNTRL0 register (address 03h)
DAC1617D1G0 3
Preliminary data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .7
Thermal characteristics . . . . . . . . . . . . . . . . . . .7
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8
Read or Write mode access description . . . . .15
Number of bytes transferred . . . . . . . . . . . . . .15
SPI timing characteristics . . . . . . . . . . . . . . . .16
Input LVDS bus swapping . . . . . . . . . . . . . . . .18
bit description . . . . . . . . . . . . . . . . . . . . . . . . .50
bit description . . . . . . . . . . . . . . . . . . . . . . . . .50
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
bit description . . . . . . . . . . . . . . . . . . . . . . . . .51
(address 09h to 0Ah) bit description . . . . . . . .52
bit description . . . . . . . . . . . . . . . . . . . . . . . . .52
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
bit description . . . . . . . . . . . . . . . . . . . . . . . . .53
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .54
bit description . . . . . . . . . . . . . . . . . . . . . . . . .57
bit description . . . . . . . . . . . . . . . . . . . . . . . . .57
bit description . . . . . . . . . . . . . . . . . . . . . . . . .57
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 39. MDS_MAN_ADJUSTDLY register (address 04h)
Table 40. MDS_AUTO_CYCLES register (address 05h)
Table 41. MDS_MISCCNTRL1 register (address 06h)
Table 42. MDS_OFFSET_DLY register (address 07h)
Table 43. MDS_ADJDELAY register (address 08h)
Table 44. MDS status registers (address 09h to 0Ah)
Table 45. Interrupt control register (address 0Bh)
Table 46. Interrupt enable register (address 0Ch)
Table 47. INTR_FLAGS register (address 0Dh)
Table 48. Bias current control registers (address 0Eh to 15h)
Table 49. Bias current control table . . . . . . . . . . . . . . . . 62
Table 50. DAC_PON_SLEEP register (address 16h)
Table 51. DAC_TEST_8 register (address 17h)
Table 52. SPI_PAGE register (address 1Fh)
Table 53. Page_0A register allocation map . . . . . . . . . . 65
Table 54. Register MAIN_CNTRL (address 00h) . . . . . . 67
Table 55. Register MAN_LDCLKDEL (address 01h) . . . 67
Table 56. Register DBG_LVDS (address 02h) . . . . . . . . 67
Table 57. Extension time reset registers
Table 58. Register DCSMU_PREDIV (address 06h) . . . 68
Table 59. LSB/MSB of polarity registers
Table 60. Register LD_CNTRL (address 0Ah) . . . . . . . . 68
Table 61. Register MISC_CNTRL (address 0Bh) . . . . . . 69
Table 62. LDS/MDS of I/Q DC levels registers
Table 63. Register IO_MUX0 and IO_MUX2
Table 64. Register IO_MUX1 and IO_MUX2
Table 65. Register TYPE_ID (address 1Bh) . . . . . . . . . . 71
Table 66. Register DAC_VERSION (address 1Ch) . . . . 72
Table 67. Register DIG_VERSION (address 1Dh) . . . . . 72
Table 68. Register LVDS_VERSION (address 1Eh) . . . . 72
Table 69. Register PAGE_ADD (address 1Fh) . . . . . . . . 72
Table 70. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 71. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 76
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64
(address 04h to 05h) bit description . . . . . . . . 68
(address 08h to 09h) bit description . . . . . . . . 68
(address 0Ch to 0Fh) bit description . . . . . . . . 70
(address 10h and 12h) . . . . . . . . . . . . . . . . . . 70
(address 11h and 12h) . . . . . . . . . . . . . . . . . . 71
DAC1617D1G0
© IDT 2012. All rights reserved.
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