DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 55

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Table 35.
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
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Page 1 register allocation map
Register name R/W
MDS_MAIN
MDS_WIN_
PERIOD_A
MDS_WIN_
PERIOD_B
MDS_
MISCCNTRL0
MDS_MAN_
ADJUSTDLY
MDS_AUTO_
CYCLES
MDS_
MISCCNTRL1
MDS_
OFFSET_DLY
MDS_
ADJDELAY
MDS_
STATUS0
MDS_
STATUS1
INTR_CTRL
INTR_EN
INTR_FLAGS
10.22.5 Page 1 allocation map
Table 35 shows an overview of all registers on page 1 (01h in hexadecimal).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RW
RW
R
R
R/W
R/W
R
MAQB_EN MAQA_EN AUTO_DL_
MDS_SR_
MDS_EQCHECK[1:0]
MAQB_
EARLY
MDS_
CKEN
Bit 7
MAN
RDY
-
-
-
-
-
MDS_SR_
LOCKOUT
MAQA_
LATE
Bit 6
RDY
-
-
-
-
ADD_ERR
SR_LOCK
DL_RDY
EQUAL
AUTO_
MDS_
MDS_
Bit 5
RUN
EN
-
-
-
AUTO_CAL
MDS_WIN_PERIOD_A[7:0]
MDS_WIN_PERIOD_B[7:0]
CAL_RDY
MDS_AUTO_CYCLES[7:0]
MDS_EQ
RELOCK
MDS_EN_PHASE[1:0]
AUTO_
EVAL_
MDS_
MDS_
MDS_
Bit 4
NCO
ENA
_EN
-
MDS_MAN_ADJUSTDLY[6:0]
Bit definition
MDS_ADJDELAY[6:0]
FLAG_DL_E
PRERUN_E
DL_ERR
EARLY_
ERROR
PULSE
FLAG_
MDS_
NCO_
MDS_
Bit 3
N
-
MDS_OFFSET_DLY[4:0]
LCLKSAMP_
LCLKSAMP_
MDS_LOCK_DELAY[3:0]
PRERUN
ERROR
CLEAR
SREF_
LATE_
INTR_
MDS_
MDS_
Bit 2
ERR
DIS
EN
MDS_PULSEWIDTH[2:0]
LOCKOUT
PARBER_
PARBER_
MASTER
EQUAL_
FOUND
MDS_
MDS_
INTR_MON_DCLK_
Bit 1
ERR
EN
RANGE
MON_DCLK
MON_DCLK
ACTIVE
MDS_
MDS_
MDS_
LOCK
_ERR
Bit 0
ENA
_EN
Default
Bin
0000
0100
1000
0000
0100
0000
0001
0000
0100
0000
1000
0000
0000
1111
0000
0000
0000
0000
uuuu
uuuu
uuuu
uuuu
0000
0100
0000
0000
uuuu
uuuu
Hex
04h
80h
40h
10h
40h
80h
0Fh
00h
00h
uuh
uuh
04h
00h
uuh
[1]