DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 17

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
10.4.1 Input port polarity
10.4.2 Input port mapping
10.4 LVDS Data Input Format (DIF) block
The Data Input Formatting (DIF) block captures and resynchronizes data on the LVDS bus
with its own LCLKP/LCLKN clock. Each LVDS input buffer has an internal resistance of
100 , so an external resistor is not required. The DIF block includes two subblocks:
The polarity of each individual LVDS input (LD[15]P to LD[0]P and LD[15]N to LD[0]N) can
be changed. This ensures a much easier PCB layout design. The input polarity is
controlled with bits LD_POL[15:0] (see Table 59).
Inverting the order of the LSB and the MSB of the LVDS bus using bit WORD_SWAP in
register LD_CNTRL (see Table 60) also simplifies the design of the PCB (see Table 9).
Fig 5.
Fig 6.
•
•
LVDS receiver:
Provides high flexibility for the LVDS interface, especially for the PCB layout and the
control of the input port polarity and the input port mapping.
Data format block:
Enables the adaptation, which ensures the support of several data encoding modes.
Power-on sequence
LVDS Data Input Format (DIF) block diagram
LD[15]N
LD[15]P
LCLKN
LCLKP
LD[0]P
LD[0]N
power supplies
RESET_N
SPI bus
Rev. 03 — 2 July 2012
RECEIVER
LVDS
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
specification
power in
range
16
16
t
on
PB[15..0]
PA[15..0]
LCLK
t
rst
WRITE DAC CONFIGURATION
START CLOCK CALIBRATION
FORMAT
t
spi_start
DATA
16
16
DAC1617D1G0
Q[15..0]
I[15..0]
001aan810
001aan392
to DAC A
to DAC B
time
© IDT 2012. All rights reserved.
17 of 78