DAC1617D1G0HN IDT [Integrated Device Technology], DAC1617D1G0HN Datasheet - Page 33

• Manufacturer Part Number: DAC1617D1G0HN
• Description: Dual 16-bit DAC, LVDS interface, up to 1 Gsps, x2, x4 and x8 interpolating
• Manufacturer: IDT [Integrated Device Technology]

Integrated Device Technology
DAC1617D1G0 3
Preliminary data sheet
Fig 24. MDS synchronization
The signal detector of the DAC1617D1G0 detects the presence of the MDS signals. Once
detected, an internal copy process of this reference starts. The MDS early/late detector
block then compares the phase difference of these two signals to align the copy to its
reference accurately. The alignment is done inside an "enabling window" that avoids the
misinterpretation of the signal edges. This alignment process is done by moving the
internal pointer of register MDS_ADJDELAY (see Table 43) (so inserting/removing a delay
in data flow). This pointer can have a preset offset. This is specified by register
MDS_OFFSET_DLY (see Table 42). Using the MDS_MAN and MDS_MAN_ADJDELAY
bits in register MDS_MAN_ADJUSTLY register (see Table 39), the alignment can also be
set manually.
Rev. 03 — 2 July 2012
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
DAC1617D1G0
© IDT 2012. All rights reserved.
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