AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet
AD9148BPCZ
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AD9148BPCZ Summary of contents
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Preliminary Technical Data FEATURES Single-carrier W-CDMA ACLR = 80 dBc @ 150 MHz IF Channel-to-channel isolation > Analog output Adjustable 8 31 Ω Ω L Novel 2×, 4×, and 8× ...
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AD9148 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4 DC Specifications ......................................................................... 4 Input/Output ...
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Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM 310MHz 310MHz –1 SINC MOD 1.2GHz DCIA_P/ DCIA_N FRAMEA_P/ FRAMEA_N 16 A[15:0]_P –1 A[15:0]_N SINC MOD –1 SINC 16 MOD B[15:0]_P/ B[15:0]_N FRAMEB_P/ FRAMEB_N DCIB_P/ ...
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AD9148 SPECIFICATIONS DC SPECIFICATIONS AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) ...
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Preliminary Technical Data INPUT/OUTPUT SIGNAL SPECIFICATIONS AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 ...
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AD9148 DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. Parameter LATENCY (DACCLK CYCLES) 1× Interpolation (With or Without Coarse Modulation) 2× Interpolation (With or Without Coarse Modulation) 4× Interpolation (With or Without Coarse Modulation) 8× Interpolation (With or Without Coarse Modulation) ...
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Preliminary Technical Data AC SPECIFICATIONS AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. Table 5. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR 400 ...
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AD9148 ABSOLUTE MAXIMUM RATINGS Table 6. With Respect To Parameter AVDD33, IOVDD AGND, DGND, CGND DVDD18, CVDD18 AGND, DGND, CGND AGND DGND, CGND DGND AGND, CGND CGND AGND, DGND I120, VREF AGND AGND OUT1_P, OUT1_N, OUT2_P, OUT2_N, OUT3_P, OUT3_N, OUT4_P, ...
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Preliminary Technical Data Table 8. Thermal Resistance and Maximum Power Package Type T (°C) PCB Layers A 196-ball CSP_BGA 85 12 196-ball CSP_BGA 85 12 196-ball BGA_EP 85 12 196-ball BGA_EP Heat sink is used in the ...
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AD9148 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUT1 AUX1 C AUX1 OUT1 CVDD18 + OUT2 OUT2 I120 ...
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Preliminary Technical Data SPI INTERFACE SDO G SDIO SCLK H J FrB DCIB K FrB DCIB IOVDD + Table 10. Pin Function Description Pin ...
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AD9148 Pin No. Mnemonic B3 AUX2_N B4 AUX2_P B11 AUX3_P B12 AUX3_N C13 AUX4_N D13 AUX4_P A8 I120 A7 VREF B6, A6 CLK_P/CLK_N B9, A9 REFCLK_P/REFCLK_N or SYNC_P/SYNC_N H4 IRQ H3 RESET G1 SDO G2 CSB H1 SDIO H2 SCLK ...
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Preliminary Technical Data Pin No. Mnemonic K11, J11 B11_P/B11_N M12, L12 B12_P/B12_N K12, J12 B13_P/B13_N M13, L13 B14_P/B14_N M14, L14 B15_P/B15_N K2, J2 DCIB_P/DCIB_N K1, J1 FRAMEB_P/FRAMEB_N Description LVDS Data Input Pair, Port B. LVDS Data Input Pair, Port B. ...
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AD9148 TYPICAL PERFORMANCE CHARACTERISTICS –30 – 200MSPS, SECOND HARMONIC DATA f = 200MSPS, THIRD HARMONIC DATA – 310MSPS, SECOND HARMONIC DATA f = 310MSPS, THIRD HARMONIC –45 DATA –50 –55 –60 –65 –70 –75 –80 –85 ...
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Preliminary Technical Data –30 –35 0dBFS, SECOND HARMONIC –6dBFS, SECOND HARMONIC –40 –12dBFS, SECOND HARMONIC –18dBFS, SECOND HARMONIC –45 –50 –55 –60 –65 –70 –75 –80 –85 – 100 150 f (MHz) OUT Figure 12. Second Harmonic vs. ...
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AD9148 –30 –35 –40 –45 – 200MSPS DATA f = 310MSPS –55 DATA –60 –65 –70 –75 –80 –85 –90 –95 –100 0 50 100 150 200 f (MHz) OUT Figure 18. IMD vs. f over f , ...
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Preliminary Technical Data –144 –146 1×, 200MSPS 2×, 200MSPS –148 4×, 200MSPS 8×, 100MSPS –150 –152 –154 –156 –158 –160 –162 –164 –166 0 50 100 150 200 250 f (MHz) OUT Figure 24. Single-Tone NSD Performance vs. f 4× ...
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AD9148 –50 –55 0dB, PLL ON 0dB, PLL OFF –60 –3dB, PLL OFF –6dB, PLL OFF –65 –70 –75 –80 –85 –90 – 100 150 200 f (MHz) OUT Figure 30. 1-Carrier W-CDMA ACLR vs. f 4× Interpolation, ...
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Preliminary Technical Data CENTER 150.00MHz #RES BW 30kHz VBW 300kHz SWEEP 193.2ms (601 PTS) TOTAL CARRIER POWER –13.30dBm/15.3600MHz REF CARRIER POWER –19.14dBm/3.84000MHz RCC FILTER: ON FILTER ALPHA 0.22 FREQ LOWER OFFSET INTEG BW dBc 5.000MHz 3.840MHz –72.59 –91.81 1 –19.14dBm ...
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AD9148 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure ...
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Preliminary Technical Data SERIAL PERIPHERAL INTERFACE SDO G1 SDIO H1 SPI PORT SCLK G2 CSB H2 t Figure 40. SPI Por The serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard micro- controllers and ...
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AD9148 SPI OPTIONS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by the LSB first bit (Register 0x00, Bit 6). The default is MSB first (LSB first = 0). When LSB first = ...
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Preliminary Technical Data SPI REGISTER MAP Table 12. Register Map Register Name Addr Bit 7 Bit 6 0x00 Comm SDIO LSB/ direction MSB first 0x01 Power Power- Power- control Down DAC Down Set 1 DAC Set 2 0x03 Data format ...
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AD9148 Register Addr Name Bit 7 Bit 6 1 0x20 Coeff I Byte0 0 1 Coeff I Byte1 Coeff_3i[2:0] 0x21 1 Coeff I Byte 2 Coeff_4i[2:0] 0x22 1 Coeff I Byte 3 0 0x23 1 Coeff Q Byte 0 0 ...
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Preliminary Technical Data Register Addr Name Bit 7 Bit 6 0x54 FTW (LSB) 0x55 FTW 0x56 FTW 0x57 FTW (MSB) 0x58 Phase offset (MSB) 0x59 Phase offset (LSB) 0x5A DDS/mod Bypass control DDS/MOD 0x5C Die Temp Control 0 0x5D Die ...
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AD9148 Addr Register Name (Hex) Bit Data Format Interrupt Enable Interrupt Enable Name Function Binary format Input data is ...
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Preliminary Technical Data Addr Register Name (Hex) Bit Event Flag 0 (All bits 06 7 are high when interrupt is active. Clear interrupt 6 by writing respective bit high Event Flag 1(All bits are 07 ...
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AD9148 Addr Register Name (Hex) Bit PLL Control 2 0D 7:6 4 3:2 1:0 PLL Status 0 0E 3:0 PLL Status 1 0F 5:0 Sync Control 2:0 Name Function N2 DAC CLK to PLL controller ...
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Preliminary Technical Data Addr Register Name (Hex) Bit Sync Control 1 11 5:0 Sync Status Data Receiver Control 14 6 Data Receiver Status FIFO status ...
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AD9148 Addr Register Name (Hex) Bit FIFO Status Port A 18 7:0 FIFO status/ 7 Control Port 2:0 FIFO Status Port B 1A 7:0 HB1 Control 2:1 0 Name Function FIFO Level ...
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Preliminary Technical Data Addr Register Name (Hex) Bit HB2 Control 0 HB3 Control 1E 7 3:1 0 Chip ID 1F 7:0 Name Function HB2[2:0] Modulation mode for second stage interpolation filter ( × HB2 IN2 000 ...
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AD9148 Addr Register Name (Hex) Bit Coeff I Byte 6:3 2:0 Coeff I Byte 1 21 7:5 4:0 Coeff I Byte 2 22 7:5 4 3:0 Coeff I Byte 6:0 Coeff Q Byte 0 ...
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Preliminary Technical Data Addr Register Name (Hex) Bit Coeff Q Byte 2 26 7:5 4 3:0 Coeff Q Byte 6:0 I Phase Adj LSB 28 7:0 I Phase Adj MSB 29 1:0 Q Phase Adj LSB 2A ...
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AD9148 Addr Register Name (Hex) Bit IDAC FSC Adj 30 7:0 IDAC Control 31 7 1:0 Aux IDAC Data 32 7:0 Aux IDAC Control 1:0 Name Function IDAC FSC Adj[7:0] IDAC full-scale current adjustment (LSB part). ...
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Preliminary Technical Data Addr Register Name (Hex) Bit QDAC FSC Adj 34 7:0 QDAC Control 35 7 1:0 Aux QDAC Data 36 7:0 Aux QDAC Control 1:0 Name Function QDAC FSC Adj[7:0] Q DAC full-scale current ...
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AD9148 Addr Register Name (Hex) Bit SED_S0_L 38 7:0 SED_S0_H 39 7:0 SED_S1_L 3A 7:0 SED_S1_H 3B 7:0 SED_S2_L 3C 7:0 SED_S2_H 3D 7:0 SED_S3_L 3E 7:0 SED_S3_H 3F 7:0 Name Function SED Compare Compare Pattern Sample0[15:0] is the word ...
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Preliminary Technical Data Addr Register Name (Hex) Bit SED Control/Status SED_R_L 41 7:0 SED_R_H 42 7:0 SED_F_L 43 7:0 SED_F_H 44 7:0 I Gain Control 50 7:0 Q Gain Control 51 7:0 ...
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AD9148 Addr Register Name (Hex) Bit FTW (LSB) 54 7:0 FTW 55 7:0 FTW 56 7:0 FTW (MSB) 57 7:0 Phase Offset MSB 58 7:0 Phase Offset LSB 59 7:0 DDS/Mod Control Die ...
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Preliminary Technical Data INPUT DATA PORTS The AD9148 can operate in three data input modes: dual-port mode, single-port mode, and byte mode. In dual-port mode, DAC 1 and DAC 2 receive data from Port A, and DAC 3 and DAC ...
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AD9148 BYTE MODE In byte mode, a FRAME signal must be provided along with the DCI signal and the data. The most significant byte of the data should correspond with DCI being high, and the least significant byte of the ...
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Preliminary Technical Data FIFO OPERATION DATA INPUT PORT A LATCH DCIA FRAME A FIFO RATE/ DATA RATE FRAME B DCIB ONE DCI INPUT DATA LATCH PORT B The AD9148 contains two 32-bit wide, 8-word deep FIFOs (one per dual DAC) ...
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AD9148 Nominally, data is written to the FIFO at the same rate as data is read from the FIFO. This keeps the data level in the FIFO constant. If data is written to the FIFO faster than data is read, ...
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Preliminary Technical Data No Synchronization In this mode, Bit 7 in Register 0x10 is set to 0, the pipeline delay in the signal processing is not controlled, and the read pointer of the FIFO is never reset. However, to assure ...
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AD9148 DEVICE SYNCHRONIZATION SYNCHRONIZING MULTIPLE DEVICES System demands may require that the outputs of multiple DACs be synchronized with each other or with a system clock. Systems that support transmit diversity or beam-forming, where multiple antennas are used to transmit ...
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Preliminary Technical Data The following procedure outlines the steps required to synchronize multiple devices. The procedure assumes that the REFCLK/SYNC signal is applied to all of the devices and the PLL of each device is phase locked to it. Each ...
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AD9148 SAMPLE RATE CLOCK SYNC CLOCK FPGA Figure 54. Typical Circuit Diagram for Synchronizing Devices to a System Clock SYNCHRONIZATION WITH DIRECT CLOCKING When directly sourcing the DAC sample rate clock to CLK, a separate SYNC input signal is required ...
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Preliminary Technical Data Figure 55 shows the synchronization signal timing with 2× interpolation, so that f = ½ × The SYNC input is shown DCI CLK equal to the DCI rate. The maximum frequency at which the device ...
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AD9148 Timing Optimization The SYNC signal is sampled by a version of the DACCLK. If sampling errors are detected, the opposite sampling edge can be selected to improve the sampling point. The sampling edge can be selected by setting Bit ...
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Preliminary Technical Data INTERFACE TIMING The timing diagram for the digital interface port is shown in Figure 58. The sampling point of the data bus nominally occurs TBD ps after each edge of the DCI signal and has an uncertainty ...
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AD9148 DIGITAL DATA PATH The block diagram in Figure 59 shows the functionality of the complex digital data path. The digital processing includes a premodulation block, a programmable complex filter, three half-band interpolation filters with built-in coarse modulation, a quadrature ...
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Preliminary Technical Data Table 17. Programmable Inverse Sinc Filter Coefficient Widths and Ranges Coefficient c in-phase (real quadrature (imaginary in-phase (real quadrature (imaginary in-phase (real quadrature (imaginary in-phase ...
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AD9148 Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 63. The shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors, the filter ...
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Preliminary Technical Data MODE 1 MODE 5 MODE 3 0 –20 –40 –60 –80 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 f (× ) IN2 Figure 66. HB2, Odd Filter Modes As shown in Figure 65 and Figure 66, ...
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AD9148 Figure 68 shows the pass-band filter response for HB3. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 23 shows the ...
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Preliminary Technical Data The NCO operating frequency the DAC rate. The NCO frequency of the complex carrier signal can be set from /2. The frequency tuning word (FTW) is calculated as DAC ...
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AD9148 CLOCK GENERATION DAC INPUT CLOCK CONFIGURATIONS The AD9148 DAC sample clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying employs the on-chip, phased-locked loop (PLL) that accepts a reference clock (REFCLK_x) operating at a submultiple of ...
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Preliminary Technical Data REFCLK_P/REFCLK_N (PIN B9 AND PIN A9) CLOCK MULTIPLICATION The on-chip PLL clock multiplier circuit can be used to generate the DAC sample rate clock from a lower frequency reference clock. When the PLL clock multiplier is enabled ...
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AD9148 Automatic VCO Band Select The device has an automatic VCO band select feature on chip; using this feature is a simple and reliable method for configuring the VCO frequency band. To use the automatic VCO band select feature, enable ...
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Preliminary Technical Data ANALOG OUTPUTS TRANSMIT DAC OPERATION Figure 75 shows a simplified block diagram of one pair of the transmit path DACs. The DAC core consists of a current source array, switch core, digital control logic, and full-scale output ...
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AD9148 Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9148 is realized when it is configured for differential operation. The common-mode error sources of the DAC outputs are reduced significantly by the common-mode rejection of a ...
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Preliminary Technical Data In addition, the output can act as a current source or a current sink. When sourcing current, the output compliance voltage 1.6 V. When sinking current, the output compliance voltage ...
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AD9148 Reducing LO Leakage and Unwanted Sidebands Analog Devices modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs as well as feedthrough paths from the LO input to ...
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Preliminary Technical Data DEVICE POWER DISSIPATION The AD9148 has four supply rails: AVDD33, IOVDD, DVDD18, and CVDD18. The AVDD33 supply powers the DAC core circuitry. The power dissipation of the AVDD33 supply rail is independent of the digital operating mode ...
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AD9148 0.35 0.30 0.25 0.20 0.15 0.10 0. 100 200 300 400 500 600 f (MSPS) DAC Figure 86. CVDD18 Power Dissipation vs. f 700 800 900 1000 Figure 87. DVDD18 Power Dissipation vs PLL Disabled ...
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Preliminary Technical Data TEMPERATURE SENSOR The AD9148 has a diode-based temperature sensor for measuring the temperature of the die. The temperature reading is accessed by Register 0x5E and Register 0x5F. The temperature of the die can be calculated as − ...
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AD9148 INTERRUPT REQUEST OPERATION The AD9148 provides an interrupt request output signal (Pin H4, IRQ ) that can be used to notify an external host processor significant device events. Upon assertion of the interrupt, the device ...
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Preliminary Technical Data INTERFACE TIMING VALIDATION The AD9148 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of ...
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AD9148 TEST ACCESS PORT The AD9148 incorporates a test access port (TAP) and boundary scan architecture. The TAP has four pins that provide access into the device for performing the boundary scan testing: • TMS ,test mode select input • ...
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Preliminary Technical Data A total of 79 pins can be accessed thru the boundary scan register. They are as follows: • A[15:0]_P, A[15:0]_N, B[15:0]_P, B[15:0]_N • DCIA_P, DCIA_N, DCIB_P, DCIB_N, • FRAMEA_P, FRAMEA_N, FRAMEB_P, FRAMEB_N • RESET E • CSB, ...
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AD9148 For the order of loading and unloading the scan chain, refer to Table 28. Table 28. TAP Load and Read Sequence TAP Load Sequence TAP Unload Sequence 0 SDIOEN SDOEN 1 SDOEN SDO 2 SDO PLL_LOCK 3 PLL_LOCK IRQ ...
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Preliminary Technical Data EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9148, certain sequences should be followed. An example start-up routine using the following device configuration is used for this example: • 122.88 MSPS DATA • Interpolation ...
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AD9148 OUTLINE DIMENSIONS A1 BALL CORNER * 1.30 1.16 1.02 12.10 12.00 SQ 11. 10.40 BSC SQ 0.80 BSC 0.80 TOP VIEW REF DETAIL A DETAIL A 0.65 REF 0.24 REF SEATING PLANE * COMPLIANT TO JEDEC ...
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... AD9148BBCZRL −40°C to +85°C AD9148BBPZ −40°C to +85°C AD9148BBPZRL −40°C to +85°C AD9148BPCZ −40°C to +85°C AD9148BPCZRL −40°C to +85°C AD9148-EBZ AD9148-M5372-EBZ AD9148-M5375-EBZ RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...