AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 43

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
No Synchronization
In this mode, Bit 7 in Register 0x10 is set to 0, the pipeline delay
in the signal processing is not controlled, and the read pointer
of the FIFO is never reset. However, to assure that the FIFO can
operate safely and there is no concurrent access to FIFO from
the write and read pointer to the same address, it is important to
ensure that the phase offset between the two pointers is greater
than 2. In consequence, the only FIFO reset that can be used
safely is the data rate synchronization, Bit 6 of Register 0x10 set
to 0, where the FIFO is reset with a fixed offset of 4 between the
write and read pointers. As there is no SYNC signal, the reset of
the FIFO write pointer can only be done by a FRAME signal or
an SPI command.
FIFO Reset Commands
Depending on the configuration of the system, the FIFO reset
could be done manually or periodically for a multichip system.
The AD9148 provides two ways to resetting the FIFO pointers:
SPI interface or periodic reset using the FRAME signal.
The SPI also gives access to each FIFO phase offset in Bits [2:0]
of the corresponding FIFO status/control registers, Address 0x17
and Address 0x19. The value in these three bits corresponds
either to the offset between the write and read pointer in the
data rate synchronization or to the absolute address of the FIFO
write pointer in the FIFO rate synchronization.
SPI Command for Manual Reset
If a manual reset is acceptable, the FIFO pointer addresses can
be reset using the SPI interface.
To initialize the FIFO data level through the SPI, Bit 3 of
Register 0x17 (FIFO Port A) or Bit 3 of Register 0x19 (FIFO
Port B) should be toggled from 0 to 1 and back. When the
write to the register is complete, the corresponding FIFO data
level is initialized.
The recommended procedure for a SPI FIFO data level
initialization is:
1.
2.
3.
Request FIFO Port A or FIFO Port B level reset by setting
Bit 3 in Register 0x17 or Bit 3 in Register 0x19 to Logic 1. The
FIFO phase offset, Bits [2:0] in Register 0x17 or Bits [2:0] in
Register 0x19 should also be written at the same time to set
the desired value of offset between the FIFO write and read
pointers.
Verify the part acknowledges the request by ensuring Bit 4
in Register 0x17 or Bit 4 in Register 0x19 is set to Logic 1.
Remove the request by resetting Bit 3, Register 0x17 or
Bit 3, Register 0x19 to 0.
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4.
Note that the SPI writes to Register 0x17 or Register 0x19
should be done while maintaining a constant value in the FIFO
phase offset bits.
FIFO Reset Using FRAME Signal
The FIFO pointers can also be reset using the FRAME signals.
If only one DCI is used, only the FRAMEA signal is used for the
FIFO reset. This mode is enabled by setting Bit 6 in Register 0x10.
As discussed in the FIFO Synchronization Modes section, the
FRAME input is used to initialize the FIFO data level value.
When the FRAME signal is asserted high for at least the time
interval needed to load the complete data to the four DACs, the
write pointer is reset depending on the mode of synchronization
chosen:
•
•
MONITORING THE FIFO STATUS
The FIFO initialization and status can be read from Register 0x17.
This register provides information about the FIFO initialization
method and whether the initialization was successful. The MSB
of Register 0x17 is a FIFO warning flag that can optionally trigger a
device IRQ. This flag is an indication that the FIFO is close to
emptying (FIFO level is 1) or overflowing (FIFO level is 7). This
is an indication that the data may soon be corrupted, and action
should be taken.
The FIFO data level can be read from Register 0x18 at any time.
The SPI reported FIFO data level is denoted as a 7-bit thermometer
code of the write counter state relative to the absolute read counter
being 0. The optimum FIFO data level of four is, therefore,
reported as a value of 00001111 in the status register.
Note that, depending on the timing relationship between DCI
and the main DACCLK, the FIFO level value can be off by a ±1
count. Therefore, it is important to keep the difference between the
read and write points to at least two.
The FIFO SPI aligned flag in the Event Flag 0 register, Bit 2
in Register 0x06, is set when the reset of the write pointer has
been realized. Bit 4 in Register 0x17 or Bit 4 in Register 0x19 is
reset to 0 to indicate which FIFO has generated this flag.
Data rate synchronization (default), Bit 6 of Register 0x10,
is set to 0. Write pointer reset to FIFO offset phase when
read pointer reaches 0.
FIFO rate synchronization, Bit 6 of Register 0x10, is set to 1.
Write pointer reset to FIFO start level on rising edge of
FRAME signal.
AD9148