AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 55

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
The NCO operating frequency, f
frequency of the complex carrier signal can be set from dc up to
f
The generated quadrature carrier signal is mixed with the I and Q
data. The quadrature products are then summed into the I and
Q data paths, as shown in Figure 70.
When using the fine modulator, the maximum signal bandwidth of
0.8 × f
Updating the Frequency Tuning Word
The frequency tuning word registers do not get updated
immediately upon writing as the other configuration registers
do. After loading the FTW registers with the desired values,
Bit 2 of Register 0x5A must transition from 0 to 1 for the new
FTW to take effect.
DAC
/2. The frequency tuning word (FTW) is calculated as
FTW
DATA
is always achieved.
=
f
CENTER
f
DAC
×
2
32
NCO
, is at the DAC rate. The
Rev. PrA | Page 55 of 73
Phase Offset Adjustment
A 16-bit phase offset may be added to the output of the phase
accumulator via the serial port. This static phase adjustment
results in an output signal that is offset by a constant angle
relative to the nominal signal. This allows the user to phase
align the NCO output with some external signal, if necessary.
This can be especially useful when NCOs of multiple AD9148s
are programmed for synchronization. The phase offset allows
for the adjustment of the output timing between the devices.
The static phase adjustment is sourced from the NCO Phase Offset
Word[15:0] value located in Register 0x58 and Register 0x59.
AD9148