AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 45

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
The following procedure outlines the steps required to
synchronize multiple devices. The procedure assumes that the
REFCLK/SYNC signal is applied to all of the devices and the
PLL of each device is phase locked to it. Each individual device
must follow this procedure.
The procedure for synchronization when using the PLL follows:
1.
2.
3.
Configure for data rate, periodic synchronization by
writing 0xC0 to the sync control register (Register 0x10).
Read the sync status register (Register 0x12) and verify that
the sync locked bit (Bit 6) is set high indicating that the
device achieved back-end synchronization and that the
sync lost bit (Bit 7) is low. These levels indicate that the
clocks are running with a constant and known phase
relative to the sync signal.
Reset the FIFO by strobing the FRAME signal high for at
least the time interval needed to load complete data to the
four DACs. Resetting the FIFO ensures that the correct
data is being read from the FIFO. This completes the
synchronization procedure, and at this stage, all devices
should be synchronized.
REFCLK(1)
REFCLK(2)
FRAME(2)
DCI(2)
t
Figure 53. Timing Diagram Required for Synchronizing Two Devices
SKEW
t
SU_DCI
Rev. PrA | Page 45 of 73
t
H_DCI
To maintain synchronization, the skew between REFCLK/SYNC
signals of the devices must be less than t
is also a setup and hold time to be observed between the DCI and
data of each device and the REFCLK/SYNC signal. When resetting
the FIFO, the FRAME signal must be held high for at least the
time interval needed to load complete data to the four DACs
(one DCI period for dual-port mode and two DCI periods for
single-port or byte mode). A timing diagram of the input signals is
shown in Figure 53.
The example in Figure 53 shows a REFCLK/SYNC frequency equal
to the data rate. While this is the most common situation, it is not
strictly required for proper synchronization. Any REFCLK/SYNC
frequency that satisfies the following equations is acceptable:
where N = 1, 2, 3, or 4.
For example, a configuration with 4× interpolation and clock
frequencies of f
f
DATA
f
= 200 MHz, f
SYNC
= f
DACCLK
VCO
/2
SYNC
= 1600 MHz, f
N
and f
= 100 MHz would be a viable solution.
SYNC
≤ f
DATA
DACCLK
SKEW
= 800 MHz, and
nanoseconds. There
AD9148