AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 28

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

AD9148
Register Name
PLL Control 2
PLL Status 0
PLL Status 1
Sync Control 0
Addr
(Hex)
0D
0E
0F
10
Bit
7:6
4
3:2
1:0
3:0
5:0
7
6
3
2:0
Name
N2
PLL cross
control enable
N0
N1
PLL control voltage
VCO band readback
Sync enable
FIFO rate/data
rate toggle
Rising edge sync
Sync averaging
Rev. PrA | Page 28 of 73
Function
DAC CLK to PLL controller clock rate (f
00 = 2.
01 = 4.
10 = 8.
11 = 16.
f
Enables PLL cross point control.
VCO to DACCLK divider.
00 = 1.
01 = 2.
10 = 4.
11 = 4.
DACCLK-to-REFCLK divider.
00 = 2.
01 = 4.
10 = 8.
11 = 16.
PLL VCO control voltage readback value.
VCO band value.
Enables synchronization logic.
Operates synchronization at the FIFO reset rate (0)/data rate (1).
Rising edge of CLK samples sync input (1), falling edge of
CLK samples sync input (0).
Average sync input of number of samples.
000 = 1.
001 = 2.
010 = 4.
011 = 8.
100 = 16.
101 = 32.
110 = 64.
111 = 128.
PC_CLK
must always be less than 50 MHz.
Preliminary Technical Data
PC_CLK
).
Default
11
001
01
Read-
only
Read-
only
0
0
1
000