AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 27

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Register Name
Event Flag 0 (All bits
are high when interrupt
is active. Clear interrupt
by writing respective
bit high.)
Event Flag 1(All bits are
high when interrupt is
active. Clear interrupt
by writing respective
bit high).
Clock receiver control
PLL Control 0
PLL Control 1
Addr
(Hex)
06
07
08
0A
0C
Bit
7
6
5
4
2
1
0
4
3
2
6
5
4
3:0
7
6
5:0
7:5
4:0
7
Name
PLL lock lost
PLL lock
Sync lock lost
Sync lock
FIFO SPI aligned
FIFO Warning 1
FIFO Warning 2
AED compare pass
AED compare fail
SED compare fail
CLK duty
correction
REFCLK duty
correction
CLK cross
correction
REFCLK cross
correction
0111
PLL enable
PLL manual
enable
Manual VCO band
PLL loop bandwidth Selects PLL loop filter bandwidth.
01001
Rev. PrA | Page 27 of 73
Function
1 = indicates that the PLL that was previously locked, has
unlocked from the reference signal.
1 = indicates that the PLL has locked to the reference clock
input.
1 = indicates that the sync logic that was previously locked,
has lost alignment.
1 = indicates that the sync logic achieved sync alignment. This
is indicated when no phase changes are requested for at least
a few full averaging cycles.
1 = indicates that a FIFO reset originating from a serial port-
based request has successfully completed.
1 = indicates that the difference between the FIFO read and
write pointers is 1.
1 = indicates that the difference between the FIFO read and
write pointers is 2.
1 = indicates that the SED logic detected a valid input data
pattern comparison against the preprogrammed expected
values.
1 = indicates that the SED logic detected an invalid input data
pattern comparison against the preprogrammed expected
values. This automatically clears when eight valid I/Q data
pairs are received.
1 = indicates that the SED logic detected an invalid input data
pattern comparison against the preprogrammed expected
values.
Enables duty-cycle correction on CLK input.
Enables duty-cycle correction on REFCLK input.
Enables differential crossing correction on CLK input.
Enables differential crossing correction on REFCLK input.
Always set these bits to 0111
Enables PLL clock multiplier.
Enables PLL band selection mode (0 = auto, and 1 = manual).
VCO band used in manual mode.
000 = narrowest bandwidth.
…
111 = widest bandwidth.
Set these bits to 01001 for optimal PLL operation.
AD9148
Default
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0111
0
1
0
110
10001