AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 29

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Register Name
Sync Control 1
Sync Status 0
Data Receiver Control
Data Receiver Status
FIFO status/
Control Port A
Addr
(Hex)
11
12
14
15
17
Bit
7
6
6
7
6
5
4
3
2
1
0
7
6
5
4
3
2:0
5:0
Name
Sync phase request
Sync Lost
Sync locked
One DCI
LVDS receiver
frame high
LVDS receiver
frame low
LVDS receiver
DCI high
LVDS receiver
DCI low
LVDS receiver
Port B high
LVDS receiver
Port B low
LVDS receiver
Port A high
LVDS receiver
Port A low
FIFO Warning 1
FIFO Warning 2
FIFO reset aligned
FIFO SPI align
acknowledge
FIFO SPI align
requesting
FIFO phase offset
Rev. PrA | Page 29 of 73
Function
Offset of internal divided by 64 clock phase after sync.
000000 = 0 DAC clocks.
…
111111 = 63 DAC clocks.
Synchronization lost.
Synchronization found.
0 = two DCIs used, DCIA_x and DCIB_x.
1 = one DCI used, DCIA_x.
Frame input LVDS level > 1.7 V.
Frame input LVDS level < 0.7 V.
DCI input LVDS level > 1.7 V.
DCI input LVDS level < 0.7 V.
Port B input LVDS level > 1.7 V.
Port B input LVDS level < 0.7 V.
Port A input LVDS level > 1.7 V.
Port A input LVDS level < 0.7 V.
FIFO read and write pointers within ±1.
FIFO read and write pointers within ±2
FIFO read and write pointers aligned after chip reset.
FIFO read and write pointers aligned after SPI driven
FIFO reset.
Request FIFO read and write pointers alignment via SPI.
FIFO read and write pointer phase offset from optimal
phase following FIFO reset.
000 = 0 offset from optimal phase.
…
111 = 7 offset from optimal phase.
The optimal value is 0.
AD9148
Default
Read-
only
Read-
only
0
Read-
only
Read-
only
Read-
only
Read-
only
Read-
only
Read-
only
Read-
only
Read-
only
Read-
only
Read-
only
Read-
only
Read-
only
0
000
000000