AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 47

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Figure 55 shows the synchronization signal timing with 2×
interpolation, so that f
equal to the DCI rate. The maximum frequency at which the device
can be resynchronized in data rate mode can be expressed as
for any positive integer, N.
Generally, for values of N equal to or greater than 3, the FIFO
rate synchronization mode is chosen.
FIFO Rate Mode Synchronization
The following procedure outlines the steps required to synchronize
multiple devices in FIFO rate mode. The procedure assumes
that the CLK and REFCLK/SYNC signals are applied to all of the
devices. Each individual device must follow the procedure.
The procedure for FIFO rate synchronization when directly
sourcing the DAC sampling clock follows:
1.
2.
3.
To ensure that each of the DACs are updated with the correct
data on the same DACCLK edge, two timing relationships must
be met on each DAC. DCI (and data) must meet the setup and
hold times with respect to the rising edge of CLK, and REFCLK/
SYNC must also meet the setup and hold time with respect to
the rising edge of CLK. When resetting the FIFO, the FRAME
signal must be held high for at least the time interval needed to
load complete data to the four DACs (one DCI period for dual-
port mode, and two DCI periods for single-port or byte mode).
When these conditions are met, the outputs of the DACs will be
updated within t
timing diagram that illustrates the timing requirements of the
input signals is shown in Figure 56.
Configure for FIFO rate, periodic synchronization by writing
0x80 to the sync control register (Register 0x10). Additional
synchronization options are available and are described in
the Additional Synchronization Features section.
Poll the sync locked bit (Bit 6, Register 0x12) to verify that
the device is back-end synchronized. A high level on this
bit indicates that the clocks are running with a constant
and known phase relative to the sync signal.
Reset the FIFO by strobing the FRAME signal high for at
least the time interval needed to load complete data to the
four DACs. Resetting the FIFO ensures that the correct
data is being read from the FIFO of each of the devices
simultaneously. This completes the synchronization
procedure, and at this stage, all devices should be
synchronized.
f
SYNC
=
f
SKEW
DATA
2
N
+ t
DCI
OUTDLY
= ½ × f
nanoseconds of each other. A
CLK
. The SYNC input is shown
Rev. PrA | Page 47 of 73
Figure 56 shows the synchronization signal timing with 2×
interpolation, so that f
equal to the FIFO rate. The maximum frequency at which the
device can be resynchronized in FIFO rate mode can be expressed as
for any positive integer, N.
ADDITIONAL SYNCHRONIZATION FEATURES
The synchronization logic incorporates additional features that
provide means for querying the status of the synchronization
and for improving the robustness of the synchronization. For
more information on these features, see the Sync Status Bits
section and the Timing Optimization section.
Sync Status Bits
When the sync locked bit (Bit 6, Register 0x12) is set, it indicates
that the synchronization logic has reached alignment. This is
determined when the clock generation state machine phase is
constant. This takes between (11 + Averaging) × 64 and (11 +
Averaging) × 128 DACCLK cycles. This bit may optionally trigger
an IRQ, as described in the Interrupt Request Operation section.
When the sync lost bit (Bit 7, Register 0x12) is set, it indicates a
previously synchronized device has lost alignment. This bit is
latched and remains set until cleared by overwriting the register.
This bit may optionally trigger an IRQ as described in the
Interrupt Request Operation section.
The sync phase readback bits (Bits [7:0], Register 0x13) report
the current clock phase in 6.2 format. Bits[7:2] report which of
the 64 states (0 to 63) the clock is currently in. When averaging
is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, and
¾). The lower two bits give an indication of timing margin
issues that may exist. If the sync sampling is error free, the
fractional clock state should be 00.
FRAME(2)
Figure 56. Synchronization Signal Timing Requirements in FIFO Rate Mode,
SYNC(2)
CLK(2)
CLK(1)
DCI(2)
f
SYNC
t
=
SKEW
8 ×
f
DATA
2
t
SU_SYNC
N
DCI
2× Interpolation
= ½ × f
t
H_SYNC
CLK
. The SYNC input is shown
AD9148