AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 57

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
CLOCK MULTIPLICATION
The on-chip PLL clock multiplier circuit can be used to generate
the DAC sample rate clock from a lower frequency reference clock.
When the PLL clock multiplier is enabled (Register 0x0A[7] = 1),
the clock multiplication circuit generates the DAC sample clock
from the lower rate REFCLK input. The functional diagram of
the clock multiplier is shown in Figure 72.
The clock multiplication circuit operates such that the VCO
outputs a frequency, f
frequency multiplied by N0 × N1.
The DAC sample clock frequency, f
The output frequency of the VCO must be chosen to keep f
the optimal operating range of 1.0 GHz to 2.1 GHz. The frequency
of the reference clock and the values of N1 and N0 must be chosen
so that the desired DACCLK frequency can be synthesized and
the VCO output frequency is in the correct range.
PLL Bias Settings
There are four bias settings for the PLL circuitry that should be
programmed to their nominal values. The PLL values shown in
Table 24 are the recommended settings for these parameters.
Table 24. PLL Settings
PLL SPI Control
PLL Loop Bandwidth
PLL Control 1 Register[4:0]
PLL Cross Control Enable
PLL Ctrl (Test) Register[7:0]
f
f
VCO
DACCLK
= f
REFCLK
= f
REFCLK
× ( N0 × N1 )
× N1
VCO
, equal to the REFCLK input signal
REFCLK_P/REFCLK_N
(PIN B9 AND PIN A9)
DACCLK
, is equal to
(PIN B6 AND PIN A6)
Figure 72. PLL Clock Multiplication Circuit
CLK_P/CLK_N
PLL LOCK LOST
VCO
Register
0x0C
0x0C
0x0D
0x79
DETECTION
PLL LOCK
0x06[7:6]
Rev. PrA | Page 57 of 73
PHASE
in
PLL ENABLE
0x0D[1:0]
0x0A[7]
÷N1
N1
FILTER
LOOP
Configuring the VCO Tuning Band
The PLL VCO has a valid operating range from approximately
1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands.
For any desired VCO output frequency, there may be several
valid PLL band select values. The frequency bands of a typical
device are shown in Figure 73. Device-to-device variations and
operating temperature affect the actual band frequency range.
Therefore, it is required that the optimal PLL band select value
be determined for each individual device.
0x0D[3:2]
÷N0
N0
PC_CLK
Address
Figure 73. PLL Lock Range Overtemperature for a Typical Device
÷N2
12
16
20
24
28
32
36
40
44
48
52
56
60
0
4
8
1000
ADC
0x0D[7:6]
N2
VCO
Bit
[7:5]
[4:0]
[4]
[7:0]
DACCLK
1200
0x0E[3:0]
PLL CONTROL
VOLTAGE
1400
VCO FREQUENCY (MHz)
1600
Optimal Setting
110
01001
1
11111111
1800
2000
AD9148
2200