AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 2

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

AD9148
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Absolute Maximum Ratings ............................................................ 8
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 20
Serial Peripheral Interface ............................................................. 21
SPI Register Map ............................................................................. 23
Input Data Ports .............................................................................. 39
FIFO Operation .............................................................................. 41
Device Synchronization ................................................................. 44
REVISION HISTORY
4/10—Revision PrA: Preliminary Version
DC Specifications ......................................................................... 4
Input/Output Signal Specifications ............................................ 5
Digital Input Data Timing Specifications ................................. 6
AC Specifications .......................................................................... 7
Thermal Resistance ...................................................................... 8
Maximum Safe Power Dissipation ............................................. 8
ESD Caution .................................................................................. 8
General Operation of the Serial Interface ............................... 21
Data Format ................................................................................ 21
SPI Pin Descriptions .................................................................. 21
SPI Options ................................................................................. 22
SPI Register Descriptions .......................................................... 25
Dual-Port Mode .......................................................................... 39
Single-Port Mode ........................................................................ 39
Byte Mode .................................................................................... 40
Data Interface Options .............................................................. 40
Synchronizing and Resetting the FIFO ................................... 42
Monitoring the FIFO Status ...................................................... 43
Rev. PrA | Page 2 of 73
Interface Timing ............................................................................. 49
Digital Data Path ............................................................................ 50
Clock Generation ........................................................................... 56
Analog Outputs............................................................................... 59
Device Power Dissipation .............................................................. 63
Temperature Sensor ....................................................................... 65
Interrupt Request Operation ........................................................ 66
Interface Timing Validation .......................................................... 67
Test Access Port .............................................................................. 68
Example Start-Up Routine ............................................................ 71
Outline Dimensions ....................................................................... 72
Synchronizing Multiple Devices .............................................. 44
Synchronization with Clock Multiplication ............................... 44
Synchronization with Direct Clocking .................................... 46
Additional Synchronization Features ...................................... 47
Premodulation ............................................................................ 50
Programmable Inverse Sinc Filter ............................................ 50
Interpolation Filters ................................................................... 51
Fine Modulation ......................................................................... 54
DAC Input Clock Configurations ............................................ 56
Driving the CLK_x and REFCLK_x Inputs ............................ 56
Direct Clocking .......................................................................... 56
Clock Multiplication .................................................................. 57
Transmit DAC Operation .......................................................... 59
Auxiliary DAC Operation ......................................................... 60
Interfacing to Modulators ......................................................... 61
Interrupt Service Routine .......................................................... 66
SED Operation ............................................................................ 67
SED Example .............................................................................. 67
Derived PLL Settings ................................................................. 71
Derived NCO Settings ............................................................... 71
Start-Up Sequence ...................................................................... 71
Device Verification Sequence ................................................... 71
Ordering Guide .......................................................................... 73
Preliminary Technical Data