AD9148BPCZ AD [Analog Devices], AD9148BPCZ Datasheet - Page 68

• Manufacturer Part Number: AD9148BPCZ
• Description: Quad 16-Bit,1 GSPS, TxDAC+ Digital-to-Analog Converter
• Manufacturer: AD [Analog Devices]

AD9148
TEST ACCESS PORT
The AD9148 incorporates a test access port (TAP) and
boundary scan architecture. The TAP has four pins that provide
access into the device for performing the boundary scan testing:
•
•
•
•
The instruction register holds the current instruction used by the
TAP controller to decide what to do with the test signals that are
received. Most commonly, the content of the instruction register
defines to which of the data registers signals should be passed.
Table 26 shows the supported instructions, the instruction code,
and the data register selected. All instruction codes that are not
listed in Table 26 are reserved.
Table 27.
Parameter
TIMING CHARACTERISTICS
SWITCHING CHARACTERISTICS
t
t
t
t
t
t
t
t
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
TMS ,test mode select input
TCK , test clock input
TDI , test data input
TDO , test data output
OUTPUTS
SYSTEM
SYSTEM
INPUTS
TCK
TMS
TDO
TDI
Figure 90. Basic Timing Diagram of the TAP Controller Signals
Description
TCK period
TDI, TMS setup before TCK high
TDI, TMS hold after TCK high
System inputs setup before TCK high
System inputs hold after TCK high
TRST pulse width (measured in TCK cycles)
TDO delay from TCK low
System output delay after TCK low
t
DSYS
t
DTDO
t
SSYS
t
STAP
Rev. PrA | Page 68 of 73
t
TCK
t
HSYS
t
HTAP
Table 26. Instruction Code Register Definition
TAP Instruction
EXTEST
IDCODE
SAMPLE/PRELOAD
BYPASS
The boundary scan register is the main test register. It provides
the means for moving data from and to the device pins. The
bypass register is a single bit register that passes data from TDI
to TDO. The IDCODE register contains the ID code and
revision number for the device. This information allows the
device to be linked to its boundary scan description language
(BSDL) file. The file contains details of the boundary scan
configuration for the device.
The content of the 32-bit IDCODE register is 0x227E51CB.
The TAP controller is reset to an inactive state by the internal
power-on-reset. Figure 90 shows the basic timing diagram of
the controller signals.
Minimum
20
4
4
4
5
4
0
Preliminary Technical Data
Instruction Code
00000
00001
00010
11111
Maximum
10
12
Data Register
Selected
Boundary scan
IDCODE
Boundary scan
Bypass
Unit
ns
ns
ns
ns
ns
TCK
ns
ns