LPC47M140-NC SMSC [SMSC Corporation], LPC47M140-NC Datasheet - Page 123
LPC47M140-NC
Manufacturer Part Number
LPC47M140-NC
Description
128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LPC47M140-NC.pdf
(205 pages)
- Current page: 123 of 205
- Download datasheet (2Mb)
zero and the RC constant (TIMA,B) pins to zero when the RC constant (TIMA,B) inputs reach 2/3 of VREF as shown.
VREF is the voltage on pin 44, which is either 5V or 3.3V. See the “VREF Pin “ section.
The game port register is defined below. It is a runtime register located at the address programmed into the base I/O
address (GAME_PORT) in Logical Device 9.
Note:
When the activate bit in Logical Device 9 is cleared, it prevents the base I/O address for the game port from being
decoded.
SMSC DS – LPC47M14X
Register 0x60 is the high byte; 0x61 is the low byte. For example, to set the primary base address to
1234h, write 12h into 0x60, and 34h into 0x61.
JOYW
TIMA,B
OUTA,B
JOYR
t1
Page 123
VREF
2
3
VREF
Rev. 03/19/2001
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