LPC47M140-NC SMSC [SMSC Corporation], LPC47M140-NC Datasheet - Page 78
![no-image](/images/no-image-200.jpg)
LPC47M140-NC
Manufacturer Part Number
LPC47M140-NC
Description
128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LPC47M140-NC.pdf
(205 pages)
- Current page: 78 of 205
- Download datasheet (2Mb)
6.9
The LPC47M14x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional
parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes.
Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel
port, and selecting the mode of operation.
The parallel port also incorporates SMSC's ChiProtect circuitry, which prevents possible damage to the parallel port due
to printer power-up.
The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated
registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP
mode. The address map of the Parallel Port is shown below:
DATA PORT
STATUS PORT
CONTROL PORT
EPP ADDR PORT
The bit map of these registers is:
Note 1: These registers are available in all modes.
Note 2: These registers are only available in EPP mode.
SMSC DS – LPC47M14X
PARALLEL PORT
DATA PORT
STATUS
PORT
CONTROL
PORT
EPP ADDR
PORT
EPP DATA
PORT 0
EPP DATA
PORT 1
EPP DATA
PORT 2
EPP DATA
PORT 3
STROBE AUTOFD
TMOUT
PD0
PD0
PD0
PD0
PD0
PD0
BASE ADDRESS + 00H
BASE ADDRESS + 01H
BASE ADDRESS + 02H
BASE ADDRESS + 03H
D0
PD1
PD1
PD1
PD1
PD1
PD1
D1
0
nINIT
PD2
PD2
PD2
PD2
PD2
PD2
D2
0
nERR
Page 78
PD3
SLC
PD3
PD3
PD3
PD3
PD3
D3
EPP DATA PORT 0
EPP DATA PORT 1
EPP DATA PORT 2
EPP DATA PORT 3
SLCT
IRQE
PD4
PD4
PD4
PD4
PD4
PD4
D4
PCD
PD5
PD5
PD5
PD5
PD5
PD5
D5
PE
nACK
PD6
PD6
PD6
PD6
PD6
PD6
D6
BASE ADDRESS + 04H
BASE ADDRESS + 05H
BASE ADDRESS + 06H
BASE ADDRESS + 07H
0
nBUSY
PD7
PD7
PD7
PD7
PD7
PD7
D7
0
NOTE
Rev. 03/19/2001
1
1
1
2
2
2
2
2
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