LPC47M140-NC SMSC [SMSC Corporation], LPC47M140-NC Datasheet - Page 163

• Manufacturer Part Number: LPC47M140-NC
• Description: 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
• Manufacturer: SMSC [SMSC Corporation]

Note:
Note:
Note 1: The default value of the DMA Channel Select register for logical device 0 (FDD) is 0x02 and for logical
Note A. Logical Device IRQ and DMA Operation
1)
SMSC DS – LPC47M14X
DMA Channel
Select
Default=0x02 or
0x04
on VCC POR,
VTR POR,
HARD RESET
and
SOFT RESET
A DMA channel is activated by setting the DMA Channel Select register to [0x01-0x03] AND :
For the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
The DMA channel must be disabled if not used/selected by any Logical Device. Refer to Note A.
device 3 and 5 is 0x04.
IRQ and DMA Enable and Disable: Any time the IRQ or DMA channel for a logical block is disabled by a
register bit in that logical block, the IRQ and/or DMA channel must be disabled. This is in addition to the IRQ
and DMA channel disabled by the Configuration Registers (active bit or address not valid).
a)
b)
c)
d)
(Note 1)
NAME
FDC: For the following cases, the IRQ and DMA channel used by the FDC are disabled. Will not
respond to the DMA request.
Digital Output Register (Base+2) bit D3 (DMAEN) set to "0".
The FDC is in power down (disabled).
Serial Ports:
Modem Control Register (MCR) Bit D2 (OUT2) - When OUT2 is a logic "0", the serial port interrupt
is disabled.
Parallel Port:
Keyboard Controller: Refer to the KBD section of this spec.
(FROM ECR REGISTER)
000
001
010
011
100
101
110
111
SPP and EPP modes: Control Port (Base+2) bit D4 (IRQE) set to "0", IRQ is disabled.
ECP Mode:
(1)
(2)
REG INDEX
0x74 (R/W)
MODE
(DMA) dmaEn from ecr register. See table.
IRQ - See table.
PRINTER
CONFIG
Bits[2:0] select the DMA Channel.
TEST
FIFO
SPP
ECP
EPP
RES
0x00= Reserved
0x01= DMA1
0x02= DMA2
0x03= DMA3
0x04-0x07= No DMA active
Page 163
CONTROLLED BY
IRQ PIN
IRQE
IRQE
IRQE
IRQE
IRQE
DEFINITION
(on)
(on)
(on)
CONTROLLED BY
PDREQ PIN
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
dmaEn
STATE
C
Rev. 03/19/2001