LPC47M140-NC SMSC [SMSC Corporation], LPC47M140-NC Datasheet - Page 19

• Manufacturer Part Number: LPC47M140-NC
• Description: 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
• Manufacturer: SMSC [SMSC Corporation]

The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are powered by VTR so that they are driven low when VCC =
0V with VTR = 3.3V. These pins will remain low following a VCC POR until serial port 2 is enabled by setting the
activate bit, at which time the pin will reflect the state of the transmit output of the Serial Port 2 block.
The following list summarizes the blocks, registers and pins that are powered by VTR.
5.8
See the “Operational Description” section for the maximum current values.
The maximum VTR current, I
3.3V). The total maximum current for the part is the unloaded value PLUS the maximum current sourced by all pins
that are driven by VTR.
GP53/TXD2(IRTX), GP60/LED1, GP61/LED2, and CLKI32. These pins, if configured as push-pull outputs, will
source a minimum of 6mA at 2.4V when driving.
5.9
The LPC47M14x offers support for Power Management Events (PMEs), also referred to as System Control Interrupt
(SCI) events. The terms PME and SCI are used synonymously throughout this document to refer to the indication of
an event to the chipset via the assertion of the nIO_PME output signal on pin 17. See the “PME Support” section.
SMSC DS – LPC47M14X
Buffers powered by VTR. GP35 and GP53 have IRTX as the alternate function and their output buffers are
powered by VTR so that the pins are always forced low when not used. GP42 is the nIO_PME pin, which is
active under VTR. GP60 and GP61 have LED as the alternate function and the logic is able to control the pin
under VTR.
USB Hub
PME interface block
PME runtime register block (includes all PME, SMI, GPIO, Fan and other miscellaneous registers)
“Wake on Specific Key” logic
LED control logic
Fan Tachometers
Pins for PME Wakeup:
Other Pins
MAXIMUM CURRENT VALUES
POWER MANAGEMENT EVENTS (PME/SCI)
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
◊
The maximum VCC current, I
(i.e., 0V or 3.3V).
The maximum VREF current, I
(i.e., 0V or 3.3V).
GP42/nIO_PME (output, buffer powered by VTR)
nRI1 (input)
GP50/nRI2 (input)
GP52/RXD2(IRRX) (input)
KDAT (input)
MDAT (input)
GPIOs (GP10-GP17, GP20-GP22, GP24-GP27, GP30-GP33, GP41, GP43, GP50-GP57, GP60, and
GP61) – all input-only except GP53, GP60, and GP61. See below.
IRTX2/GP35 (output, buffer powered by VTR)
GP53/TXD2(IRTX) (output, buffer powered by VTR)
GP60/LED1 (output, buffer powered by VTR)
GP61/LED2 (output, buffer powered by VTR)
The pins that are powered by VTR are as follows:
TR
, is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0V or
CC
REF
, is given with all outputs open (not loaded) , and all inputs in a fixed state
, is given with all outputs open (not loaded) , and all inputs in a fixed state
Page 19
GP42/nIO_PME, IRTX2/GP35,
Rev. 03/19/2001