LPC47M140-NC SMSC [SMSC Corporation], LPC47M140-NC Datasheet - Page 70

• Manufacturer Part Number: LPC47M140-NC
• Description: 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
• Manufacturer: SMSC [SMSC Corporation]

SMSC DS – LPC47M14X
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 7: The UART1 and UART2 FCR’s are shadowed in the UART1 FIFO Control Shadow Register (runtime
ADDR = 6
ADDR = 7
ADDR = 0
ADDR = 1
DLAB = 1
DLAB = 1
Data Bit 2
Data Bit 2
Enable
Receiver Line
Status
Interrupt
(ELSI)
Interrupt ID Bit Interrupt ID Bit
XMIT
Reset
Number
Stop
(STB)
OUT1
(Note 3)
Parity
(PE)
Trailing Edge
Ring Indicator
(TERI)
Bit 2
Bit 2
Bit 10
ADDRESS*
REGISTER
register at offset 0x20) and UART2 FIFO Control Shadow Register (runtime register at offset 0x21).
BIT 2
Table 33 – Register Summary for an Individual UART Channel (continued)
FIFO
Error
Bits
of
Data Bit 3
Data Bit 3
Enable
MODEM
Status
Interrupt
(EMSI)
(Note 5)
DMA
Select
6)
Parity Enable
(PEN)
OUT2
(Note 3)
Framing Error
(FE)
Delta
Carrier Detect
(DDCD)
Bit 3
Bit 3
Bit 11
MODEM Status Register
Scratch Register (Note 4)
Divisor Latch (LS)
Divisor Latch (MS)
BIT 3
Mode
(Note
Data
REGISTER NAME
Data Bit 4
Data Bit 4
0
0
Reserved
Even
Select (EPS)
Loop
Break
Interrupt (BI)
Clear to Send
(CTS)
Bit 4
Bit 4
Bit 12
BIT 4
Parity
Page 70
Data Bit 5
Data Bit 5
0
Reserved
Stick Parity
0
Transmitter
Holding
Register
(THRE)
Data
Ready (DSR)
0
Bit 5
Bit 5
Bit 13
BIT 5
REGISTER
SYMBOL
MSR
SCR
DLM
DDL
Set
Data Bit 6
Data Bit 6
0
FIFOs
Enabled
(Note 5)
RCVR Trigger
LSB
Set Break
0
Transmitter
Empty (TEMT)
(Note 2)
Ring Indicator
(RI)
Bit 6
Bit 6
Bit 14
Delta Clear
to Send
(DCTS)
Bit 0
Bit 0
Bit 8
BIT 6
BIT 0
Data Bit 7
Data Bit 7
0
FIFOs
Enabled
(Note 5)
RCVR Trigger
MSB
Divisor Latch
Access
(DLAB)
0
Error in RCVR
FIFO (Note 5)
Data
Detect (DCD)
Bit 7
Bit 15
Bit 7
Bit 9
Delta Data
Set Ready
(DDSR)
Bit 1
Bit 1
BIT 7
BIT 1
Carrier
Bit
Rev. 03/19/2001