HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 1040

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Module
Port C
Port D
Port E
Port F
Port G
Notes: 1. Lower 16 bits of the address.
Rev.4.00 Sep. 07, 2007 Page 1010 of 1210
REJ09B0245-0400
2. Only 0 can be written for flag clearing.
3. Registers in the DTC cannot be read or written to directly.
4. Located as register information in on-chip RAM addresses H'EBC0 to H'EFBF. Cannot
5. The initial value differs depending on the MCU operating mode.
6. Bits used for pulse output cannot be written to.
7. If the pulse output group 2 and pulse output group 3 output triggers are the same
8. Only 0 can be written to bits 7 to 5, to clear the flags.
be located in external memory space. Do not clear the RAME bit in SYSCR to 0 when
using the DTC.
according to the PCR setting, the NDRH address will be H'FF4C, and if different, the
address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different,
the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
Register
Port C data direction register
Port C data register
Port C register
Port C MOS pull-up control register PCPCR
Port D data direction register
Port D data register
Port D register
Port D MOS pull-up control register PDPCR
Port E data direction register
Port E data register
Port E register
Port E MOS pull-up control register PEPCR
Port F data direction register
Port F data register
Port F register
Port function control register 2
System control register
Port G data direction register
Port G data register
Port G register
Port function control register 2
Abbreviation R/W
PCDDR
PCDR
PORTC
PDDDR
PDDR
PORTD
PEDDR
PEDR
PORTE
PFDDR
PFDR
PORTF
PFCR2
SYSCR
PGDDR
PGDR
PORTG
PFCR2
W
R/W
R
R/W
W
R/W
R
R/W
W
R/W
R
R/W
W
R/W
R
R/W
R/W
W
R/W
R
R/W
Initial Value Address *
H'00
H'00
Undefined
H'00
H'00
H'00
Undefined
H'00
H'00
H'00
Undefined
H'00
H'80/H'00 *
H'00
Undefined
H'30
H'01
H'10/H'00
*
H'00 *
Undefined *
H'30
5
*
20
20
5
20
H'FEBB
H'FF6B
H'FF5B
H'FF72
H'FEBC
H'FF6C
H'FF5C
H'FF73
H'FEBD
H'FF6D
H'FF5D
H'FF74
H'FEBE
H'FF6E
H'FF5E
H'FFAC
H'FF39
H'FEBF
H'FF6F
H'FF5F
H'FFAC
1