HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 348

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HD6412332

Manufacturer Part Number
HD6412332
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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8.3.8
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. It is also possible, by setting both the CHNE bit and CHNS
bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. SAR,
DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
Figure 8.9 shows the memory map for chain transfer.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Rev.4.00 Sep. 07, 2007 Page 318 of 1210
REJ09B0245-0400
DTC vector
address
Chain Transfer
Register information
start address
Figure 8.9 Chain Transfer Memory Map
Register information
Register information
CHNE = 1
CHNE = 0
Destination
Destination
Source
Source

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