HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 95

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

2.8.6
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode,
software standby mode, and hardware standby mode. There are also two other power-down
modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other
bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation
of individual modules, other than the CPU. For details, refer to section 21, Power-Down Modes.
(1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while
the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep
mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of
CPU registers are retained.
(2) Software Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the
CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the
contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their
existing states.
(3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY
pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop.
The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip
RAM contents are retained.
2.9
2.9.1
The CPU is driven by a system clock, denoted by the symbol φ. The period from one rising edge
of φ to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or
three states. Different methods are used to access on-chip memory, on-chip supporting modules,
and the external address space.
2.9.2
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 2.14 shows the on-chip memory access cycle. Figure 2.15 shows
the pin states.
Power-Down State
Basic Timing
Overview
On-Chip Memory (ROM, RAM)
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