HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 301

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the
DREQ pin is selected to 1.
Figure 7.23 shows an example of DREQ pin falling edge activated normal mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA write cycle ends, acceptance
resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of φ starts.
[4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
φ
DREQ
Address
bus
DMA
control
Channel
Figure 7.23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of φ,
and the request is held.
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of φ, and the request is held.)
Idle
[1]
Request
Bus release
of 2 cycles
Minimum
[2]
Read
[3]
Transfer source
Request clear period
DMA
read
Write
Transfer destination
Acceptance resumes
DMA
write
Idle
[4]
Request
of 2 cycles
Minimum
release
Rev.4.00 Sep. 07, 2007 Page 271 of 1210
Bus
[5]
Read
[6]
Transfer source
Request clear period
DMA
read
Write
Transfer destination
Acceptance resumes
REJ09B0245-0400
DMA
write
Idle
[7]
release
Bus