HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 226

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HD6412332

Manufacturer Part Number
HD6412332
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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6.10.4
Figure 6.37 shows the timing for transition to the bus-released state.
Rev.4.00 Sep. 07, 2007 Page 196 of 1210
REJ09B0245-0400
Address
bus
Data bus
AS
RD
HWR,
LWR
BREQ
BACK
BREQO*
[1] Low level of BREQ pin is sampled at fall of T
[2] BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master.
[3] BREQ pin state is still sampled in external-bus-released state.
[4] High level of BREQ pin is sampled.
[5] BACK pin is driven high, ending bus release cycle.
[6] BREQO signal goes high 1.5 clocks after rise of BACK signal.
Note: * Output only when BREQOE = 1.
φ
Transition Timing
T
0
CPU cycle
Figure 6.37 Bus-Released State Transition Timing
T
Address
1
[1]
Minimum
1 state
T
2
[2]
2
state.
External-bus-released state
[3]
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
[5]
CPU cycle
[6]

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