HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 1045

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HD6412332

Manufacturer Part Number
HD6412332
Description
Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet

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TCR3—Timer Control Register 3
Bit
Initial value
Read/Write
:
:
:
CCLR2
R/W
7
0
Notes: 1.
Counter Clear
0
1
CCLR1
R/W
0
1
0
1
6
0
2.
Synchronous operation setting is performed by setting the SYNC
bit in TSYR to 1.
When TGRC or TGRD is used as a buffer register, TCNT is not
cleared because the buffer register setting has priority, and
compare match/input capture does not occur.
0
1
0
1
0
1
0
1
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture
TCNT cleared by TGRD compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
CCLR0
R/W
5
0
CKEG1
Clock Edge
R/W
0
1
4
0
0
1
CKEG0
R/W
Count at rising edge
Count at falling edge
Count at both edges
3
0
Timer Prescaler
Rev.4.00 Sep. 07, 2007 Page 1015 of 1210
H'FE80
0
1
0
1
0
1
TPSC2
R/W
2
0
0
1
0
1
0
1
0
1
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
Internal clock: counts on φ/1024
Internal clock: counts on φ/256
Internal clock: counts on φ/4096
TPSC1
R/W
1
0
*2
*2
TPSC0
*1
*1
R/W
0
0
REJ09B0245-0400
TPU3

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