HYB39S64160AT-10 SIEMENS [Siemens Semiconductor Group], HYB39S64160AT-10 Datasheet - Page 18

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HYB39S64160AT-10

Manufacturer Part Number
HYB39S64160AT-10
Description
64 MBit Synchronous DRAM
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have V
3. If clock rising time is longer than 1 ns, a time (t
4. If tT is longer than 1 ns, a time (t
5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock,
Semiconductor Group
crossover point. The transition time is measured between V
with the AC output load circuit shown in fig.1. Specified tac and toh parameters are measured with a 50 pF only,
without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V..
as follows:
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit
command is registered.
OUTPUT
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
CLOCK
INPUT
tSETUP
tHOLD
tLZ
tAC
1.5V
T
tCL
-1) ns has to be added to this parameter.
tCH
tOH
il
tAC
= 0.4 V and V
t
tHZ
T
T
/2 - 0.5) ns has to be added to this parameter.
2.4 V
0.4 V
18
1.5V
ih
ih
= 2.4 V with the timing referenced to the 1.5 V
and V
64MBit Synchronous DRAM
HYB39S64400/800/160AT(L)
fig.1
il
I/O
. All AC measurements assume t
Measurement conditions for
I/O
Z=50 Ohm
tac and toh
50 pF
+ 1.5 V
50 Ohm
50 pF
T
=1ns

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